I am working on the TSE currently.
I generated the IP and configured it to RGMII. I am providing all clk signals 125MHz with a pll. And I did the following configuration (same as the generated tb):
0x02: 0400803b (MAC loop enabled)
And when I send packets to the TSE, ff_tx empty&full related fifo signals works, which means the fifo is receiving packets from my side.
But the tx_control and the rgmii_out signals are always 0s.
Also the ff_rx signals never changes.
Could anyone tell me where the problem is? I configured everything as the example, but the signals don't reacts as the example...
It seems like you are trying to bring up TSE IP by referencing to certain example design but it's not working.
May I know which FPGA that you are using and which example design that you refer to ?
Just to confirm you are running simulation and not hardware testing right ?
Have you tried to verify the example design instead of your own design ? Then you can compare the difference and it may lead to the actual root cause.
Sorry I was not explaining clearly. I am using Altera Cyclone V and Quartus 15.1.
I generated the TSE IP and generated the example design at the last step of the IP.
I ran the simulation for the example in Modelsim and everything worked fine.
Then I created my design and tested it on hardware.
I set the all the configurations as the example in my design. But I got the problem I described earlier.
Hope you can help!
The other thing is are you using Intel FPGA CV dev kit board or your own board for hardware testing ?
I dig some search and found out we do have application note doc providing CV TSE RGMII reference design (page 16) and guideline on how to perform internal MAC loopback test (page 17)
This will be a good start to try bring up TSE IP using golden reference design first then only slowly port over to test your own design.
I am using my own board for hardware testing. I used the board for other projects and I am sure the reset and clock signals works fine.
Thank you for your reference design provided I will check with that.
One concern is I checked the modelsim test bench. The data sending to the TSE only has a Ethernet header and then then the data 0x0102030405.... There is no 3 or 4th layer header(IPv4 or UDP/TCP something) for the data. Do you think that's a problem (I am thinking maybe the TSE detects the packet is not a valid IP data, and drops it)?
In my hardware test, the empty signal of the TSE fifo goes low (indicating data received), and then goes high after several clocks. I assume it dropped the packet since it is not a valid one?
I presume you are using signal_tap to probe on RGMII interface. I dig further and found out this is not possible due to this is hard circuitry path in silicon where signal probing is not possible. Refer to KDB link below.
TSE MAC won’t analyze or process 3th or 4th layer info as those are info required by upper layer analysis only. If you refer to AN647, Ethernet packet generator is just generating PRBS data pattern to TSE MAC only.
I suspect below are the 3 reasons causing TSE MAC loopback to fail on your hardware board assuming clock and reset are fine as per your feedback earlier.
Thank you again for your information. It really helped a lot!
After checking everything as you suggested. I found where the problems were:
Next I think I need to config the PHY correctly and everything should be fine.