Tristate Bridge Problem

Altera_Forum · ‎08-26-2006

I have component sram_0 (16 bits width) and flash_0 (8 bits width) share a tristate bridge data bus.

How can I assign both tri_state_bridge_0_data to both components' data bus

during instantiation using VHDL?

If i write tri_state_bridge_0_data(7 downto 0)=>fl_dq

and tri_state_bridge_0_data (15 downto 0) =>sram_dq(15 downto 0)

it wil generate compiling error..... http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/sad.gif

Altera_Forum · ‎08-27-2006

You can use the SOPC build your tri_bridge design.

Using SRAM and CFI IP core, will output FL_CS_n , FL_RD_n , FL_WR_n , SRAM_CS_n , SRAM_RD_n ,and SRAM_WR_n .

RD_n <= FL_RD_n and SRAM_RD_n ;

WR_n <= FL_WR_n and SRAM_WR_n ;

You can try!

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originally posted by kwchiet@Aug 26 2006, 09:30 AM

i have component sram_0 (16 bits width) and flash_0 (8 bits width) share a tristate bridge data bus.

how can i assign both tri_state_bridge_0_data to both components' data bus

during instantiation using vhdl?

if i write tri_state_bridge_0_data(7 DOWNTO 0)=>FL_DQ[/b]

and tri_state_bridge_0_data (15 downto 0) =>sram_dq(15 downto 0)

it wil generate compiling error..... http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/sad.gif

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