Nios® V/II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® V/II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
12589 Discussions

Tristate bridge controller parameters

Altera_Forum
Honored Contributor II
1,054 Views

Hi all, 

I'm working in migrate an old project based on QSYS on Quartus 11.00. 

Checking and fixing some issues on the constraints I've try review also if the parameters for the SSRAM and the flash were correctly assigned (they gave some problems in the past) and I'm stuck to understand the meaning of these parameters: 

 

read wait time = 0 !! 

write wait time = 0 ! 

setup time = 0 ! 

... 

 

The parameters are set by default selecting the cypress memory (or any other memory on the right) but they don't match with the meaning and what I would expect from the description. 

Looking at chapter 2 of the AVALON TRI-STATE COMPONENT USER GUIDE (page 2-5), i woudl have expect a minimum of 1 and not 0. 

Someone can help me to understand?  

As example how I should set them for a mem that has the following read and write timing? 

 

https://alteraforum.com/forum/attachment.php?attachmentid=14482&stc=1 https://alteraforum.com/forum/attachment.php?attachmentid=14483&stc=1  

https://alteraforum.com/forum/attachment.php?attachmentid=14481&stc=1 https://alteraforum.com/forum/attachment.php?attachmentid=14481&stc=1 Ale
0 Kudos
0 Replies
Reply