UART IP - waitrequest signal

[Patrik78]

Hello to everybody,

working with Platform Designer (Quartus 21.1) I'm facing something strange: I'm trying to interface the UART CORE IP with a custom hardware. But I noticed the IP is missing any flowcontrol signals.

So how to understand if the UART has received something, possibly avoid polling technique ? 

As far as I know the old dataready signal is now deprecated, and is suggested to use waitrequest signal. But it seems even this signal is not implemented in the standard UART IP.

Trying to connect my custom hardware with UART IP I get this message "Interconnect is inserted between master and slave, because master has waitrequest signal 1 bit wide, but slave is 0 bit wide" 

Moreover what if I want to connect directly to a DMA ?

Thanks for your help.

[aikeu]

Hi Patrik78,

I will get back to you regarding the info to your question.

Thanks.

Regards,

Aik Eu

[aikeu]

Hi Patrik78,

There is a flow control available in the UART core IP.

You can enable the CTS/RTS in the settings of the UART core IP.

There is no waitrequest signal to be considered for this IP.

Refer to the embedded peripherals IP user guide for the description of it's operation:

https://www.intel.com/content/www/us/en/docs/programmable/683130/21-2/introduction.html

Thanks.

Regards,

Aik Eu

[aikeu]

FYI, the enablement of the CTS/RTS in the IP settings.

Thanks.

Regards,

Aik Eu

[Patrik78]

Hi Aik,

actually RTS and CTS are signals on UART side, my goal is to get flow control signals on Avalon side.

In other words a standard avalon interface is not able to know if the IP has received data from uart side, except for polling technique.

[aikeu]

Hi Patrik78,

I am consulting engineering at the moment for that particular IP. It will take some time for respond. Sorry for the inconvenience.

Thanks.

Regards,

Aik Eu

[aikeu]

Hi Patrik78,

The control register bit of the UART IP, IRRDY will required to be enabled if using interrupt instead of a polling technique.

"irrdy - Enable interrupt for a receive character ready"

the irq is sent to the HPS side, which has an interrupt receiver port

There is no port to detect the interrupt in the avalon interface side.

Besides that, user can consider using a new Lightweight UART IP (releasing in 22.3) which having TXFIFO and RXFIFO. With this, a DMA is not required

Thanks.

Regards,

Aik Eu

[aikeu]

Hi Patrik78,

Do you have any further question regarding the previous comment?

Thanks.

Regards,

Aik Eu

[aikeu]

Hi Patrik78,

I will close this thread if no further question.

Thanks.

Regards,

Aik Eu

[Patrik78]

Hello,

if I understand correctly, there's no way to use the UART IP with DMA except the use of a device with HPS.

This is really a bad thing to hear, but ok I have no other question.

[aikeu]

Hi Patrik78,

Sorry that I mentioned incorrectly about HPS as your system which is using Nios ii.

The irq should be sent to the Nios ii interrupt reciver port.

The control register bit of the UART IP, IRRDY will required to be enabled if using interrupt instead of a polling technique.

"irrdy - Enable interrupt for a receive character ready"

Thanks.

Regards,

Aik Eu

[Patrik78]

Hello,

yes I understand the point, and how to handle the UART by interrupt with the NIOS II.

But regarding the original question, there's no way to connect to a DMA using an handshake technique.

As DMA is not able to handle IRQ signal, there's no way to make a working connection between UART and DMA.

Is this correct ?

[aikeu]

Hi Patrik78,

I think an interrupt request can be used to initiate a request for DMA operation else it will be relying on polling method to perform the DMA operation.

Thanks.

Regards,

Aik Eu

[aikeu]

Hi Patrik78,

The DMA controller and UART IP can actually work together which does not require an interrupt.

Communication wise, the DMA has multiple channel, where UART is configured to one of the channel to trigger a specific DMA channel to read or write data

therefore, no need of interrupt or to disturb the core.

Polling or interrupt method is only applicable when core (processor) is involved

Thanks.

Regards,

Aik Eu

[aikeu]

Hi Patrik78,

I will close this thread for now. Do consider create a new thread if there is further question.

Thanks.

Regards,

Aik Eu