Hi all,I'm trying to simulate the Altera's UART IP... As for the TX path, it works perfectly - I write the data via Avalon interface to address 0x01 and UART transmits it. In the testbench, I connect the UART RX directly to UART TX. So I expected that UART should receive the same data as it transmitted. But this doesn't happen - UART just receive nothing... It seems it even doesn't detect that something is coming on its RX... So, should this loopback (RX directly connected to TX) work in the simulation? Have someone simulated this IP? Thank you!
Hi, which FPGA are you using? I am using the Cyclone V SoC and trying to assign the UART_RX and UART_TX signals to "special function" pins, but I am unable to do so.