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UART with FIFO Buffer

Altera_Forum
Honored Contributor I
2,342 Views

Need to use UART with FIFO Buffer in SOPC Builder Nios II System: 

 

1> The UART RS232 available in SOPC are without FIFO is it possible to add FIFO by modifying the same UART core 

2> If not is there any other SOPC ready UART_FIFO core available as free IP 

3> If not is it possible to get estimate of 

- LE utilization without Modem Control logic 

- Is it necessary to write device driver for the same  

- Apprx how much design time it will take to  

design HDL UART, device driver for a single person? 

 

Please advice asap. running short of time. 

 

Thanks in Advance
0 Kudos
27 Replies
Altera_Forum
Honored Contributor I
414 Views

 

--- Quote Start ---  

originally posted by rau@Oct 24 2005, 09:16 AM 

need to use uart with fifo buffer in sopc builder nios ii system: 

 

1> the uart rs232 available in sopc are without fifo is it possible to add fifo by modifying the same uart core 

2> if not is there any other sopc ready uart_fifo core available as free ip 

3> if not is it possible to get estimate of 

  - le utilization without modem control logic 

  - is it necessary to write device driver for the same  

  - apprx how much design time it will take to  

    design hdl uart, device driver for a single person? 

 

please advice asap. running short of time. 

 

thanks in advance 

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=10542) 

--- quote end ---  

 

--- Quote End ---  

 

 

 

Hi  

i think in sopc builder when we instantiate uart 

we get tab which asks for fifo size as it is in built. 

but i don&#39;t understand why u need another fifo  

for a uart.anyway i don&#39;t think it may be required. 

 

prasad
Altera_Forum
Honored Contributor I
414 Views

 

--- Quote Start ---  

originally posted by rau+oct 24 2005, 09:16 am--><div class='quotetop'>quote (rau @ oct 24 2005, 09:16 am)</div> 

--- quote start ---  

1> the uart rs232 available in sopc are without fifo is it possible to add fifo by modifying the same uart core[/b] 

--- quote end ---  

 

that uart&#39;s code is generated on-the-fly by the sopc builder, so you could modify it, but it would be tricky, and you&#39;d have to figure out a way to keep your changes from being overwritten when the sopc gets regenerated. good luck there. 

 

 

--- quote start ---  

originally posted by rau@oct 24 2005, 09:16 am 

2> if not is there any other sopc ready uart_fifo core available as free ip 

--- quote end ---  

 

not that i&#39;m aware of. there are free cores, and cores that integrate with sopc builder, but not both. 

 

 

--- quote start ---  

originally posted by rau@oct 24 2005, 09:16 am 

3> if not is it possible to get estimate of 

  - le utilization without modem control logic 

--- quote end ---  

 

usually the ip data sheet gives some clue to this. 

 

 

--- quote start ---  

originally posted by rau@oct 24 2005, 09:16 am 

  - is it necessary to write device driver for the same 

--- quote end ---  

 

maybe. assume it&#39;s going to need a driver unless you can find one out there already. 

 

 

--- quote start ---  

originally posted by rau@oct 24 2005, 09:16 am 

  - apprx how much design time it will take to  

    design hdl uart, device driver for a single person? 

--- quote end ---  

 

a while. this depends on many unmeasurable factors, so i couldn&#39;t give you a number. but it won&#39;t be easy. 

 

<!--quotebegin-prasad_forums@Oct 26 2005, 01:03 AM 

i think in sopc builder when we instantiate uart 

we get tab which asks for fifo size as it is in built. 

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=10579) 

--- quote end ---  

 

--- Quote End ---  

 

Really? I&#39;ve never seen that. However, I&#39;ve only used the Nios2 Altera UART, not any other core. Maybe you&#39;re thinking of the JTAG UART?
Altera_Forum
Honored Contributor I
414 Views

Hallo rau, 

 

there is a free UART16550 core from OpenCores that can simply be implemented in a NIOS design and it is also not that problem to implement it into the SOPC Builder. All you have to do is to import the top level design file into the SOPC builder using the "Create new component feature" or to write your own bus wrapper to connect the WISHBONE bus to the AVALON.  

 

You will find this core here: 

 

opencores uart16550 (http://www.opencores.com/projects.cgi/web/uart16550/overview

 

More work has to be done to write some driver software for it. The register structure of this UART is also really simple so that it should only take a short time to bring something up to work. 

 

Best regards... 

 

Mschulz.
Altera_Forum
Honored Contributor I
414 Views

There is a uart with fifo which Altera sent me when I was having troubles with the standard uart speed. The file is ACF2002.zip which I am sure you can ask for from the service request people. 

 

You need unzip it and add this whole directory to this location: <NiosII Installation Path>/components/. Then you can reopen the SOPC Builder to add this UART with fifo. 

It comes up as "cal uart". 

Good luck 

Ed
praveenkumar
Beginner
250 Views

please send the file to  mail @praveentatikonda2155@gmail.com

Altera_Forum
Honored Contributor I
414 Views

dear Edmund, 

Could you give the file ,thanks ,my email:nwpu_zhfeng@126.com
Altera_Forum
Honored Contributor I
414 Views

Thanks for all the i/ps. 

On my way to design UART with FIFO which will be included in Nios sys. 

In case of any difficulties/problems will keep coming back 

 

Thanks and Regards 

 

 

--- Quote Start ---  

originally posted by mike desimone+oct 27 2005, 12:44 am--><div class='quotetop'>quote (mike desimone @ oct 27 2005, 12:44 am)</div> 

--- quote start ---  

 

--- quote start ---  

originally posted by rau@oct 24 2005, 09:16 am 

1> the uart rs232 available in sopc are without fifo is it possible to add fifo by modifying the same uart core 

--- quote end ---  

 

that uart&#39;s code is generated on-the-fly by the sopc builder, so you could modify it, but it would be tricky, and you&#39;d have to figure out a way to keep your changes from being overwritten when the sopc gets regenerated. good luck there. 

 

 

--- quote start ---  

originally posted by rau@oct 24 2005, 09:16 am 

2> if not is there any other sopc ready uart_fifo core available as free ip 

--- quote end ---  

 

not that i&#39;m aware of. there are free cores, and cores that integrate with sopc builder, but not both. 

 

 

--- quote start ---  

originally posted by rau@oct 24 2005, 09:16 am 

3> if not is it possible to get estimate of 

     - le utilization without modem control logic 

--- quote end ---  

 

usually the ip data sheet gives some clue to this. 

 

 

--- quote start ---  

originally posted by rau@oct 24 2005, 09:16 am 

     - is it necessary to write device driver for the same 

--- quote end ---  

 

maybe. assume it&#39;s going to need a driver unless you can find one out there already. 

 

 

--- quote start ---  

originally posted by rau@oct 24 2005, 09:16 am 

     - apprx how much design time it will take to  

       design hdl uart, device driver for a single person? 

--- quote end ---  

 

a while. this depends on many unmeasurable factors, so i couldn&#39;t give you a number. but it won&#39;t be easy. 

 

<!--quotebegin-prasad_forums@Oct 26 2005, 01:03 AM 

i think in sopc builder when we instantiate uart 

we get tab which asks for fifo size as it is in built. 

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=10579) 

--- quote end ---  

 

--- Quote End ---  

 

Really? I&#39;ve never seen that. However, I&#39;ve only used the Nios2 Altera UART, not any other core. Maybe you&#39;re thinking of the JTAG UART? 

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=10611)</div> 

[/b] 

--- Quote End ---  

Altera_Forum
Honored Contributor I
414 Views

dear Edmund, 

Could you give the file ,thanks you very much! 

my email: wfeiwu@21cn.com 

Best Regards, 

feiwu
Altera_Forum
Honored Contributor I
414 Views

 

--- Quote Start ---  

originally posted by feiwu@Nov 23 2005, 01:19 PM 

dear edmund, 

could you give the file ,thanks you very much! 

my email:  wfeiwu@21cn.com 

best regards, 

feiwu 

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=11105) 

--- quote end ---  

 

--- Quote End ---  

 

 

I have finished designing the UART having with FIFO without FIFO mode. 

the components/entities are as follows: 

Reciver State Machines - 1.write cycle 

2.read cycle 

Receiver Shift Register, Receiver FIFO and data register 

Transmitter State Machines - 1.Write cycle for Data register and FIFO + Read cycle 

for Data 

2.read cycle for FIFO 

3.shifting data out 

Transmitter FIFO and data register, Receiver shift register 

Register Bank 

Register select logic 

and Baud rate generator 

 

I need a clarification: 

The Baud rate generator is generating a clock from the system clock. 

 

I am using baud clock for  

Transmitter shift register 

and transmitter state machine 3 for shifting data out 

rest all transmitter aoperation is on system clock i.e. TXFIFO uses single clock 

 

In RX logic 

baud clock is used for RXshift register to shift in the data and for the state machine that controls shifting in the data and writing to FIFO/data register 

ie. RX state machine 1 

the RXFIFO and receiver state machine controlling the read cycle work on system clock. 

 

I need confirmation that ifthe way I am using baud clock and the system clock is correct? 

 

regards
Altera_Forum
Honored Contributor I
414 Views

Edmund 

 

I also have the same problem. Could you please email it to victors@mweb.co.za
Altera_Forum
Honored Contributor I
414 Views

Hallo Edmund, 

 

is it also possible, that I can get the ZIP file for the FIFO UART? 

 

Thanks, M.Schulz.
Altera_Forum
Honored Contributor I
414 Views

Dear everyone, 

Who has used the CAL_UART successfully? 

Could you please tell me how to use it in uClinux ? 

Best Regards, 

Fei Wu
Altera_Forum
Honored Contributor I
414 Views

Hi Edmund, 

 

I have the same problem. Could you pls email the file to... 

hootsmon1 at hotmail dot com 

 

**edited ** Got it now, thanks all
Altera_Forum
Honored Contributor I
414 Views

I have the same problem. Could you pls email the file to me: r_wa@sina.com

thanks.
Altera_Forum
Honored Contributor I
414 Views

Hi all, 

 

for information, the cal_uart is not performant unless you make some modifications. Actually, it works correctly in poll mode, not with interrupts. The reason for this is that the interrupts are not generated correctly, and can freeze the system (I use it mainly under uClinux, I don&#39;t know the HAL driver very well). 

A first fix to this is to change 

<cal_uart>/uart_pm.pl:l1933:rx_char_ready to rx_not_empty 

This will generate the IRQ properly (regarding to avalon spec), but will not take advantage of the FIFO (IRQ when 1 byte is in the FIFO, which is not optimized). I changed the VHDL to take full advantage of the FIFO, i.e. generate IRQ when FIFO is half full, or every xx ms if a char is present in FIFO. 

All this is explained in the "cal_uart(with fifo) + NIOSserial.c" thread in uClinux forum. 

 

Hope this helps, 

 

Regards, 

 

Pierre-Olivier
Altera_Forum
Honored Contributor I
414 Views

These work great! and integrate with SOPC builder very easily (instructions included work great!). 

 

http://forum.niosforum.com/forum/index.php?showtopic=4120 (http://forum.niosforum.com/forum/index.php?showtopic=4120

 

I have tested it out and find no problems.
Altera_Forum
Honored Contributor I
414 Views

Dear Edmund 

Could you give the file ^^ 

 

My Email pearlt@chol.com 

 

thanks for your help^^
Altera_Forum
Honored Contributor I
414 Views

Hi,pearlt. 

I read about the UART with FIFO you requested to Edmund. 

Did you receive that? Can you send me too? 

My email is 

 

tonelli.paolo@gmail.com 

 

Many thanks in advance.
Altera_Forum
Honored Contributor I
414 Views
Altera_Forum
Honored Contributor I
414 Views

Oh,many thanks Slaker.Now,it&#39;s ok. 

I hope this will be easy to use as get it through your link http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/laugh.gif
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