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Uart Baud Rate Drop

Altera_Forum
Honored Contributor II
905 Views

Hi all 

 

I'm currently facing a somehow strange effect on my custom SoC Board (incl. a Cyclone V SX --> 5CSXFC2C6U23C8(N)).  

While the preloader and uboot are running (at the moment initialized by the DS-5 Debugger over JTAG) I can verify them by UART prompt (8-N-1, baud 115200). As soon as I kill the connection and start my bare metal application (In this case a simple hello world printing via printf (-DPRINTF_UART used for the compile) I receive garbage on the prompt.  

 

So far I have verified the baud rate during the boot process with a oscilloscope --> baud = 116100 Hz (guess +/-3% are ok!) 

When I measure the frequency while the bare metal application prints I see a frequency of: baud = 92000 Hz 

 

This is somehow strange as the baud rate is defined by a divisor and the L4_SP_clk frequency (100MHz) which in my opinion are not changing between those two processes. I also tested the exact same setup with the Cyclone V Soc Development Board and never saw any of this happen.  

 

Has anyone experienced some similar situations? Please let me know if you need more information!  

 

Best 

 

Stefan
0 Kudos
4 Replies
Altera_Forum
Honored Contributor II
134 Views

Stefan, 

 

You should double check the PLL and divisors settings for the L4 clock. 

This looks to me when you use DS5, a different spl gets loaded, and its L4 setting are not the same ones as U-Boot. 

 

Regards
Altera_Forum
Honored Contributor II
134 Views

Hi Eric, 

 

Thank you for your reply.  

I'm actually using the spl and the u-boot image from the same compile (by using the commands "make all" and "make uboot") and both are loaded via DS-5 since the SD-card seems to fail. 

 

How can I check on the L4 settings (except the ones I can set in Qsys) and the divisors? I guess it has to be somewhere in the spl / uboot src code but I've only found the settings in socfpga_common.h: 

 

* * L4 OSC1 Timer 0 */ /* This timer use eosc1 where the clock frequency is fixed * throughout any condition */# define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS /* reload value when timer count to zero */# define TIMER_LOAD_VAL 0xFFFFFFFF /* Timer info */# define CONFIG_SYS_HZ 1000 /* Clocks source frequency to timer */# if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)# define CONFIG_TIMER_CLOCK_KHZ 2400# else /* Preloader and U-Boot need to know the clock source frequency from handoff*/# define CONFIG_TIMER_CLOCK_KHZ (CONFIG_HPS_CLK_OSC1_HZ / 1000)# endif  

 

The EOSC1 frequency is running on a 20MHz quartz (in comparison to the Development board where it is running at 25MHz). 

 

EDIT: 

While reading the pll_config.h file I found the following settings: 

# ifndef _PRELOADER_PLL_CONFIG_H_# define _PRELOADER_PLL_CONFIG_H_ # define CONFIG_HPS_DBCTRL_STAYOSC1 (1) # define CONFIG_HPS_MAINPLLGRP_VCO_DENOM (0)# define CONFIG_HPS_MAINPLLGRP_VCO_NUMER (59)# define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT (0)# define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT (0)# define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT (0)# define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT (511)# define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT (511)# define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT (11)# define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK (1)# define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK (1)# define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK (0)# define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK (0)# define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK (0)# define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK (1)# define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK (0)# define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP (1)# define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP (1) # define CONFIG_HPS_PERPLLGRP_VCO_DENOM (0)# define CONFIG_HPS_PERPLLGRP_VCO_NUMER (49)# define CONFIG_HPS_PERPLLGRP_VCO_PSRC (0)# define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT (511)# define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT (511)# define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT (511)# define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT (4)# define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT (9)# define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT (511)# define CONFIG_HPS_PERPLLGRP_DIV_USBCLK (4)# define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK (4)# define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK (4)# define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK (4)# define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK (3124)# define CONFIG_HPS_PERPLLGRP_SRC_SDMMC (2)# define CONFIG_HPS_PERPLLGRP_SRC_NAND (2)# define CONFIG_HPS_PERPLLGRP_SRC_QSPI (1) # define CONFIG_HPS_SDRPLLGRP_VCO_DENOM (0)# define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (15)# define CONFIG_HPS_SDRPLLGRP_VCO_SSRC (0)# define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT (1)# define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE (0)# define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT (0)# define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE (0)# define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT (1)# define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE (4)# define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT (5)# define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE (0) # define CONFIG_HPS_CLK_OSC1_HZ (20000000)# define CONFIG_HPS_CLK_OSC2_HZ (20000000)# define CONFIG_HPS_CLK_F2S_SDR_REF_HZ (0)# define CONFIG_HPS_CLK_F2S_PER_REF_HZ (0)# define CONFIG_HPS_CLK_MAINVCO_HZ (1200000000)# define CONFIG_HPS_CLK_PERVCO_HZ (1000000000)# define CONFIG_HPS_CLK_SDRVCO_HZ (320000000)# define CONFIG_HPS_CLK_EMAC0_HZ (1953125)# define CONFIG_HPS_CLK_EMAC1_HZ (1953125)# define CONFIG_HPS_CLK_USBCLK_HZ (6250000)# define CONFIG_HPS_CLK_NAND_HZ (50000000)# define CONFIG_HPS_CLK_SDMMC_HZ (200000000)# define CONFIG_HPS_CLK_QSPI_HZ (2343750)# define CONFIG_HPS_CLK_SPIM_HZ (6250000)# define CONFIG_HPS_CLK_CAN0_HZ (6250000)# define CONFIG_HPS_CLK_CAN1_HZ (6250000)# define CONFIG_HPS_CLK_GPIODB_HZ (32000)# define CONFIG_HPS_CLK_L4_MP_HZ (100000000)# define CONFIG_HPS_CLK_L4_SP_HZ (100000000) # define CONFIG_HPS_ALTERAGRP_MPUCLK (1)# define CONFIG_HPS_ALTERAGRP_MAINCLK (3)# define CONFIG_HPS_ALTERAGRP_DBGATCLK (3) # endif /* _PRELOADER_PLL_CONFIG_H_ */  

 

Have you been referring to that?  

 

Thanks again for your time, I really appreciate your help! 

 

Regards 

 

Stefan
Altera_Forum
Honored Contributor II
134 Views

Stefan, 

 

Reading the Muxes, PLL & Divisor values directly from the clock manager registers will provide you with the exact UART clock frequency. 

If you have the hwLib, you can simplify this by using alt_clk_freq_get(): this function reads the clock manager registers and report the resulting clock frequency. 

 

Regards
Altera_Forum
Honored Contributor II
134 Views

Stefan, 

 

make sure you set-up / build / use the correct external crystal frequency according to the target platform. 

You have 25 MHz and 20 MHz 

92160 == (115200 * 20) / 25 

 

Regards
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