Unable to get Nios-II F going, Nios-II S works fine in same config. (DE2-115 + SDRAM)

Altera_Forum · ‎11-24-2017

Hello All,

I have a DE2-115 running a Nios-II S(low) with the on board SDRAM (basic config, HELLO WORLD application). 50 Mhz clock, 3ns delay for the ram clock, no FPGA RAM used.

When I change to Nios-II-F(ast), using the same configuration I am unable to start the CPU (an exception is thrown at startup).

I wonder what can be the reason ?

What is a bit strange is that the OpenCore dialog box (Quartus Lite Edition 17.0) does not come up when I download. I know that the Slow CPU does not need the Open Core licence (as it seems), but I thought that the F version did.

If so, how can I convince Quartus to launch OpenCore upon download of my VHDL project ?

To be sure there are no hickups in Eclipse, I generate a new program based on the SOPC file generated by QSYS, so I do not use an updated BSP to start from when changing the CPU type. The old configuration cannot pollute the new one.

The exact error I get is that Nios throws an exception and ends up at Nios2_BREAK() (alt_instruction_exception_entry.c). This after I oblige eclipse to download by overruling the timpmestamp check that is not correct.) Since I generated a brand new file based on a newly generated Sopc file, this also seems very strange. Iam also very sure I download the correct version to my FPGA board. (tried it multiple times)

Backtracking on the stack, the exception seems to be generated in alt_get_fd.c, getting a descriptor for my Jtag Uart. Very strange because for the -S CPU this works properly ? The exact line is line 79 where alt_fd_list.dev is accessed.

for (i = 0; i < alt_max_fd; i++)

{

if (!alt_fd_list.dev) <= this line

{

alt_fd_list[i].dev = dev;

if (i > alt_max_fd)

{

alt_max_fd = i;

}

rc = i;

goto alt_get_fd_exit;

}

Is there anybody who got the -F cpu working on an SDRAM config for the DE2-115 in a Quartus lite config?

Is anybody able to explain what I did wrong or forgot ?

Thanks for any advice,

Johi.

Altera_Forum · ‎11-25-2017

Dear All,

My mistake:

You can select 2 different versions of the .sof file to download to the FPGA.

The standard version

The time limited version.

For the /f cpu you need the time limited version in Q lite.

And for those of you struggeling with a DE2-115 Nios-II/F.

I included a Q17.0 archive of my working project.

Best Regards,

Johi.