We are rapidly changing the NIOS SW without any changes in FPGA programmable logic.
Is there a way to say to Quartus do not to change (do not touch) the FPGA programmable logic at all and only update the FPGA part, which is strictly related to NIOS SW?
For example using Nios II Processor Booting from QSPI Flash:
If you scroll down 1 page (276), you can see that once you generated the .sof file (Quartus compile), you can reuse the .sopcinfo from the compiled design, and generate the .pof from the .sof.
You can proceed and repeat just from the steps "BSP Editor Settings".
Cool... So, as for the JIC generation, should both SOF and HEX files be the input files?
What actually happens during the JIC file generation? How does it mix the SOF and HEX files?
Yes, the .sof, .hex are the input files, and the .pof generated:
See the example here:
OK, the *.POF is for MAX devices... What's the flow for the *.JIC devices (e.g. Cyclone 10)?
Should not I deal with a bootloader in order to load two images from FLASH (the first image is for FPGA programming, the second one is for NIOS SW)?
I suggest that you refer to the documentation, and follow the steps and try it on your board.
If you require to test another design, you can try below: