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Altera_Forum
Honored Contributor I
1,328 Views

Usage of pipeline bridge and clock crossing bridge

Hello, 

 

I have a Nios II processor which should access some peripherals. Is there a rule for how to place the pipline bridge and the clock crossing bridge. My system looks like this currently: 

 

Nios II | |- Pipeline Bridge | |- Clock Crossing Bridge | |- Peripheral 1 |- Peripheral 2 |- Peripheral 3 ...  

 

Does the order of the placement of the Clock Crossing Bridge and Pipeline Bridge matter? Could this setup also make sense?: 

 

Nios II | |- Clock Crossing Bridge | |- Pipeline Bridge | |- Peripheral 1 |- Peripheral 2 |- Peripheral 3 ...  

 

Regards 

Martin
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3 Replies
Altera_Forum
Honored Contributor I
191 Views

Here's the response I got from the Altera support regarding this questioin: 

 

There is no a rule for how to place the pipeline bridge and the clock crossing bridge, this is all depend on your design requirement and how are you going to optimizing the system. You can refer to the following link page 8 (“using Bridges”). 

http://www.altera.com/literature/hb/qts/qsys_optimize.pdf
Altera_Forum
Honored Contributor I
191 Views

You don't always need bridges. SOPC Builder and QSys can connect Avalon Memory mapped masters and slaves that use different clocks and will add some clock domain crossing logic f needed, so you could just make your system without any bridges. Such a solution is rather slow though, as it can't pipeline several requests between the two clock domains. So such a solution is fine if the master only does single access from time to time (a PIO register, for example) but if you need a higher throughput, then you should add a clock crossing bridge. 

For the pipeline bridges, you can start first without them and check if you pass the timing requirements. Their main purpose is to add a pipeline stage and can be useful when lots of components are connected together (lots of slaves on one master, lots of masters on one slave, or any combination of the above). I usually find it simpler to first compile a design without pipeline bridges, and then check with Timequest where the failing paths are and add pipeline bridges only on those paths, until I meet the timing requirements.
Altera_Forum
Honored Contributor I
191 Views

There is no easy answer to the question. Each bridge serves a different purpose so I would only add them when needed. For example if you have the clock crossing bridge in your system and you are having troubles meeting timing between the bridge and other masters in the system then it might make sense to insert the pipeline bridge. Keep in mind that as you add in these bridges the latency of the accesses downstream from the bridges will also increase so you need to carefully examine your system to determine what frequencies *and* latencies make sense for your design.

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