Nios® II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
12453 Discussions

Use SDRAM from SoC and VHDL component

Altera_Forum
Honored Contributor II
1,140 Views

Hi 

I have SDRAM Controller connected to HPS and i want to use SDRAM (to read/wite) also from my VHDL component. Unfortunately during compilation I get error that says there can by only one signal connected to SDRAM. How to resolve that?
0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
108 Views

I assume you are not talking about the HPS SDRAM controller and you have a second one instantiated in the FPGA. All it should take is connecting the HPS-to-FPGA bridge and your user logic master to that memory in Qsys. 

 

Now if you are trying to connect to the HPS SDRAM controller then your logic in the FPGA has to connect to the FPGA-to-SDRAM interface of the HPS which will then arbitrate between masters in the HPS and your FPGA logic. 

 

I'm having a hard time visualizing how you are arriving at this error message so maybe a screenshot of your system in Qsys would help fill in the dots.
Reply