Use SDRAM from SoC and VHDL component

[Altera_Forum]

Hi 

I have SDRAM Controller connected to HPS and i want to use SDRAM (to read/wite) also from my VHDL component. Unfortunately during compilation I get error that says there can by only one signal connected to SDRAM. How to resolve that?

[Altera_Forum]

I assume you are not talking about the HPS SDRAM controller and you have a second one instantiated in the FPGA. All it should take is connecting the HPS-to-FPGA bridge and your user logic master to that memory in Qsys. 

 Now if you are trying to connect to the HPS SDRAM controller then your logic in the FPGA has to connect to the FPGA-to-SDRAM interface of the HPS which will then arbitrate between masters in the HPS and your FPGA logic.  I'm having a hard time visualizing how you are arriving at this error message so maybe a screenshot of your system in Qsys would help fill in the dots.