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Altera_Forum
Honored Contributor I
1,089 Views

Using EPCQ to load Nios

1) Why can't I get past "No EPCS registers found"? 

If I try "nios2-flash-programmer --device=1 --base=0x42000000 --epcs --debug" 

I get: 

Using cable "USB-Blaster [USB-0]", device 1, instance 0x00 

Resetting and pausing target processor: OK 

Processor data bus width is 32 bits 

Looking for EPCS registers at address 0x42000000 (with 32bit alignment) 

Initial values: 01000098 0000203A 01883A01 42370100 3A010880 01C8B388 

Not here: reserved fields are non-zero 

Looking for EPCS registers at address 0x42000100 (with 32bit alignment) 

Initial values: 01000098 0000203A 01883A01 42370100 3A010880 01C8B388 

Not here: reserved fields are non-zero 

Looking for EPCS registers at address 0x42000200 (with 32bit alignment) 

Initial values: 01000098 0000203A 01883A01 42370100 3A010880 01C8B388 

Not here: reserved fields are non-zero 

Looking for EPCS registers at address 0x42000300 (with 32bit alignment) 

Initial values: 01000098 0000203A 01883A01 42370100 3A010880 01C8B388 

Not here: reserved fields are non-zero 

Looking for EPCS registers at address 0x42000400 (with 32bit alignment) 

Initial values: 01000098 0000203A 01883A01 42370100 3A010880 01C8B388 

Not here: reserved fields are non-zero 

No EPCS registers found: tried looking at addresses 

0x42000000, 0x42000100, 0x42000200, 0x42000300 and 0x42000400 

Leaving target processor paused 

 

Now, I've read various other threads and app notes and have done the following: 

My EPCS controller has reset connected to system reset and Nios JTAG Debug port reset. 

My EPCS controller is clocked with a 25 MHz clock. 

My NIOS processor is clocked with a 25 MHz clock. 

0x42000000 is the address base for the EPCS CSR bus, but it does the same if I use 0x41000000 which is the memory base. 

I can program the EPCS device using a JIC file for the FPGA program, but was hoping to use nios2-flash-programmer to get a software image on there because that doesn't erase the whole device each time. So I know the EPCS device can be programmed via JTAG, and I know the FPGA can boot from it as it recognises my NIOS processor. 

 

2) When I started this post I had assumed I'd got past question 1, but sadly not. Question 2 is - am I really forced to run the NIOS at 25MHz because the EPCS controller is limited to 25MHz? Does QSYS not put in a clock crossing buffer if I have NIOS running at 100MHz and EPCS at 25MHz? It's going to make everything else run very slowly if I'm forced to run NIOS at 25MHz. 

 

Any clues gratefully received.
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5 Replies
Altera_Forum
Honored Contributor I
99 Views

1) Make sure the EPCS pins are configured to be used as general purpose I/O in the Quartus device settings. Otherwise the fpga can properly load the hardware configuration but then the pins are not accessible by Nios or any other 'soft' device. 

 

2) Sure you can run Nios at 100MHz (or whatever f you need) and keep EPCS at 25MHz: this is a quite common configuration. 

You simply need a PLL to generate the 2 clocks and a clock crossing bridge between the two sections in Qsys.
Altera_Forum
Honored Contributor I
99 Views

 

--- Quote Start ---  

1) Make sure the EPCS pins are configured to be used as general purpose I/O in the Quartus device settings. Otherwise the fpga can properly load the hardware configuration but then the pins are not accessible by Nios or any other 'soft' device. 

 

2) Sure you can run Nios at 100MHz (or whatever f you need) and keep EPCS at 25MHz: this is a quite common configuration. 

You simply need a PLL to generate the 2 clocks and a clock crossing bridge between the two sections in Qsys. 

--- Quote End ---  

 

Thanks for the quick reply. 

 

I am struggling with your first suggestion - If I open up quartus, and go Assignments->Device then Device and Pin Options. 

There seems no where I can set general purpose I/O - on dual purpose pins I only get offered Data 15..8 and Data 7..5 - not the EPCQ pins.
Altera_Forum
Honored Contributor I
99 Views

Hmm..you are using Nios II Flash Programmer. Could you switch to Quartus II Programmer to flash your epcs? 

 

Which device are you using?  

 

Refer to this document: https://www.altera.com/en_us/pdfs/literature/an/an736.pdf
Altera_Forum
Honored Contributor I
99 Views

Thanks for your reply. I don't want to use Quartus II Programmer because 

a) I don't want the whole chip to be erased each time I program, 

b) I want the NIOS Cpu to be able to program the EPCQ flash itself, and so the nios2-flash-programmer has to work. 

 

I'm using a Cyclone V 5CSTFD5D5 part. 

 

I have read an736, thank you. Is there any particular part you wanted to refer to? 

 

I think the pertinent point was from Cris72, when he said the EPCS pins need to be configured as general purpose I/O - but Quartus 15.1 doesn't let me do that.
Altera_Forum
Honored Contributor I
99 Views

Hi, 

 

It sounds a bit confusing to me. Are you using EPCS or EPCQ? 

The nios2-flash-programmer should works fine for EPCS but it may not work well for certain EPCQ devices with larger memory >256Mb. 

 

Regards, 

CH
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