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Altera_Forum
Honored Contributor I
1,244 Views

Using EPCS and CFI for booting - failure

Hi guys, 

 

I'm in a real trouble and now after 5 days still do not see any solution. The situation is that I have a an eval board from EVB with CIII. On the board there is an EPCS and a CFI flash. The whole design contains a NIOS with some simple test software. My intention was to store the FPGA design in to the EPCS and the NIOS software into the CFI. Of course the CFI has a 3state bridge populated, the reset vector points to CFI flash. Everything made by the Altera's instructions. I've created the JIC file, and programmed into the EPCS w/Quartus programmer. Then in the NIOS EDS (or Eclipse or whatever) edited the system, set .rodata and .text to CFI_FLASH segment, all the others point to some on-chip or external volatile memory. Invoked flash programmer and load the system settings, the software observed the EPCS and the CFI so created 2 tabs. On the EPCS I added the sof file (btw. I do not understand this, if I programmed already the JIC file in Quartus, why do I need to used the SOF here again?) and on the CFI tab I added the elf file. Set converting, programming erase before program, etc. Hit start then it was done w/o any error. Attached is the log in pdf format.  

 

Again one comment, if I'm the boss of a sw developer team where someone produces a software w/o the opportunity to save the log, I'm sure I would break that guy's hand, then fire. But minimum drink his blood until he implements this feature. Eh... 

 

Cycling the power the system won't boot. Nothing happens. It looks like to be dead. But if I use the Run as NIOS hardware, it works perfectly. This means for me, that the FPGA configuration code is well written into the EPCS, only the CFI writing was not perfect on some reason. When I make it run it proves that all the IPs have set correctly. The code runs in the CFI well, I have heap from the sdram, and so on. LED blinks, whatever you like. 

 

I've tried 9.1 SP2, 10.1. SP1, 11.0, same effect. I was browsing on the forum a lot but found no solution. 

 

Can anyone of you guys help me to fix this problem before I go totally crazy here? Many thanks in advance!
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7 Replies
Altera_Forum
Honored Contributor I
113 Views

Hi alibiman: 

 

My guess is the nios boot loader is looking at the epcs instead of the CFI flash. 

 

Have you tried loading a small "led blink" style program into the EPCS instead of the CFI? 

 

If that works, you could write a small bootloader that's stored in the EPCS that then causes the CFI flash to be loaded and started. 

 

Pete
Altera_Forum
Honored Contributor I
113 Views

Interesting idea, I will check this. However I do not understand then the purpose of boot loader program: C:/ALTERA/91/nios2eds/components/altera_nios2/boot_loader_cfi.srec. There is a reference for that in the properties.

Altera_Forum
Honored Contributor I
113 Views

Yes, I'm not too familiar with the nios boot loader, but the "Reset" vector will make a difference. 

 

I would check the CPU settings and make sure the reset vector is looking at the CFI. If so I'm stuck, I would try to build in a signal tap and track where the CPU was fetching the first few instructions. 

 

 

I've only dealt with a system that had EPCS memory for booting. 

 

Pete
Altera_Forum
Honored Contributor I
113 Views

Yes I agree... Open SOPC builder, and in the CPU settings check the value of the reset vector. If it's on the EPCS controller, then the CPU will start a bootloader that will look for the application in the EPCS flash.

Altera_Forum
Honored Contributor I
113 Views

Quote from my post: 

 

"Of course the CFI has a 3state bridge populated, the reset vector points to CFI flash." 

 

:)
Altera_Forum
Honored Contributor I
113 Views

I don't know how I missed that... sorry :( 

I don't remeber how it actually works, but there is an option in signaltap to record some signals during the FPGA startup. You should include a signaltap probe on the CPU's data and instruction masters to try and find out what the CPU is doing when it starts, and include it in the configuration you flash in the EPCS. There is an option somewhere to enable so that the probe starts recording as soon as the FPGA goes into user mode, and then you can fire the signaltap application to download the buffer. Hopefully it will help you understand if the CPU is trying to start the application or is stuck somewhere.
Altera_Forum
Honored Contributor I
113 Views

Ok, I have found the solution, so I describe it here. Finally will be a compact description about the how to. 

 

But first about the Altera support. Here is the thread, shame... 

 

Q: Was the same as the post here, how to boot form CFI, etc. 

A: The linker sections such as .text, .rodata, .heap and .etc should be mapped to volatile region of system memory, and not to the flash memory. 

 

Q: If the reset vector points to ext_flash, how can be the .text in volatile region? 

A: When the reset vector is set to non-volatile memory such as ext_flash, a CFI boot loader provided by Altera will be automatically included. During the conversion of .elf to .flash (elf2flash in flash programming), it will pack the application code in the boot record, and then creates a .flash file containing the boot loader and the boot record. During flash programming, it downloads this boot record to your CFI flash memory (ext_flash). The boot loader is located at Altera installation directory, e.g. 

d:\altera\11.0\nios2eds\components\altera_nios2 

 

Therefore, on the next power cycle of the board, the Nios II processor will reset itself from ext_flash and the boot loader executes, reads the boot record and then copies the application code to volatile memory (the memory where you assign to the .text linker section). After copying is complete, the boot loader reads the entry point of the application code from the boot record. The boot loader executes the jump to that address, and the application software begins executing. 

 

(So the guy states that is not possible to run from flash, instead it will run in some RAM) 

 

Q: This is not good for me. I want the application to run in ext_flash. How can I do that? 

A: Nope 

 

Q: the suggestion you wrote seems does not work. If I set the .text segment to other than EXT_FLASH I egt an error message in flash programmer: elf2flash: Boot copier overlaps data in flash. 

Any clue? 

A: There are extra cares need to be taken if you are booting and running from same memory i.e. ext_flash because the application's .text section is not copied. I encourage you to refer to pg. 52 - Booting and Running From Flash Memory for the care and setting that you need. 

http://www.altera.com/literature/hb/nios2/edh_ed51002.pdf 

The error is probably you have other sections that are still assigned to ext_flash. To avoid this error, please assign all the .text to memory other than ext_flash. 

 

And here the matter, the solution comes, in the pdf he suggests. Well here are the steps how to run from CFI, etc. 

 

1. Create your NIOS system, add CFI and EPCS stufds. do not forget to set the reset vector to the cfi flash. 

2. Assemble your hardware in Quartusimodo. Generate the .sof file. Program it, do not convert to jic, or pof or whatever. 

3. Load NIOS EDS (Eclipse), write your software. Generate the system and here: 

- set the .text to CFI flash 

- set the .rodata (optional) to CFI flash. 

- all the others should stay in volatile memory, onchip, sdram, etc. 

- in the pdf file above, on the page# 53, the table 2-2 gives the solution

4. Invoke the Flash programmer. If you see the USB Blaster (or eq. loader) then OK, if you do not, then go back to Quartusimodo and program again the sof file. 

5. Menu, hit "New", choose a the "BSP setting file" and seek for the file <your projectdir\software\blablablabla_bsp>\settings.bsp. If you really installed CFI and EPCS then you will get TWO tabs. One for EPCS one for CFI. 

6. Choose EPCS, click add, and search for your sof file (your hardware). Note, if your HW is final, so you modify only the SW from now, you need to flash the epcs only once. That will be burned forever (up to the next HW design change). 

7. Choose the CFI tab, seek for the elf file, typically in <your projectdir\software\blablablabla>\whatever.elf. You do not need to modify anything. 

8. If you like, you can set in the Options menu erase before flash, etc. 

9. Hit START button, ...and wait for the strike back. :-P 

10. Cycle the power and voila: the system will boot. 

 

Note that: IS faster to flash your HW compilation from NIOS EDS than in the Quartusimodo (convert to JIC, etc). 

 

What I hate very much in the Altera's techsup and literature stocking, that if there is any problem: 

 

1. MySupport does not understand the question. 

2. If understands, then answers stupidity. 

3. If is not able the answer any useful then the client has to hunt for some info on the web. This is a real scatter-gather job, because several informations dealing with the same problem circle are cut into small slices into 12448781214 pdf files. Very hard to find the necessary information, almost impossible. 

 

I am loosing my hair.
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