Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Altera_Forum
Honored Contributor I
1,103 Views

Using Nios II with PLL

Hello there, 

 

so I´m trying to generate 100MHz from 50MHz via the ALTPLL in Qsys and use that 100MHz to speed up the NiosII. 

 

Unfortunately its not working... 

Im Using a 10M16DCF256I7 and 10M16SAE144I7G (maybe the FPGAs are not powerful enough?) 

 

These are the steps in Qsys: 

 

1. Add ALTPLL --> Simple without locked etc. and a factor of 2 

2. 50 Mhz Input clock connected to ALTPLL 

3. Add Nios System and connect it with the ALTPLL outputclock 

4. peripherals like System ID , JTAG, PIO etc. 

5. Design Synthesis 

6. Connect clock input 

7. Flash sof 

8. Trying to flash hello_world_small.c 

9. Fail.... unable to restart 

 

 

Thanks in advance ;)
0 Kudos
6 Replies
Altera_Forum
Honored Contributor I
137 Views

Will your logic run at 100MHz? Have you constrained your project, told Quartus about the 50MHz clock and derived clocks? Did Quartus report it could meet timing? 

 

Those devices can and will run logic at 100MHz, depending on the complexity of the design. Qsys systems with a Nios processor can result in (relatively) complex logic that simply may not run at 100MHz. If so, I'm afraid it's not going to work. 

 

Ensure you've constrained your design and note whether it meets timing - having run it through Quartus. 

 

Cheers, 

Alex
Altera_Forum
Honored Contributor I
137 Views

Thank you very much for your response, 

 

i created a sdc file with those parameters:  

 

create_clock -name {CLOCK50MHz} -period 20.000 [get_ports { clk_clk }] 

derive_clock_uncertainty 

derive_pll_clocks 

 

The TimeQuest report says, that fmax could be 117 MHz on the PLL Clock and 250MHz on the input clock 

 

*the logic only consists of the nios system there is nothing else in the design
Altera_Forum
Honored Contributor I
137 Views

Does exactly the same Qsys system work if you simply change the PLL multiplier to 1 instead of 2? You state it's "unable to restart". How are you judging that? No 'Hello world' console message or an Eclipse system message? Is your console connected via JTAG? Can any of the PIO output signals be made to work? 

 

Cheers, 

Alex
Altera_Forum
Honored Contributor I
137 Views

Hi Alex, 

 

didnt thought of that... But it doesnt work either.  

The Console is connected via JTAG and the hello world small works without the PLL.... 

 

Using cable "USB-Blaster [USB-0]", device 1, instance 0x00 

Pausing target processor: not responding. 

Resetting and trying again: FAILED 

Leaving target processor paused 

 

This is the output of Eclipse... 

 

For futher diagnosis the whole project is attached. 

This Project is made with a EP4CE10F17C8N but is also ported to a MAX10 and isn´t working either 

 

That you very much.
Altera_Forum
Honored Contributor I
137 Views

OK - the project you attached fundamentally works - more or less... 

 

I ported it to a DE0-Nano with no changes, except for the device and pinout. In doing so I notice you'd exported the PLL's reset ("altpll_0_areset_conduit_export") but not constrained it to a pin. So, Quartus has chosen a pin which, I suspect, you're not controlling. So, it's probably pulled high holding the PLL in reset. 

 

I connected that to a switch and proved this. Providing the PLL is out of reset (reset driven LOW), the processor boots and "hallo Welt>!Init Phase...." is written to the console. I'm confident (although I didn't try it) that it will work at 100MHz as well. 

 

I expect you have the same issue with your MAX 10 project. 

 

Cheers, 

Alex
Altera_Forum
Honored Contributor I
137 Views

Hi there,  

Thank you very much you helped me a lot!
Reply