Using Scaler II with NIOS II

[Altera_Forum]

Hello, 

 I've got problem using the Scaler II from the vip suite with Nios II. It seems that my attempt to write to the scaler's register fail everytime I try.  Once the megacore is stopped, I send new values to registers with this function :  alt_u32 ALT_VIP_SCALER_II_WRDATA(alt_u32 vipBaseAddress, alt_u32 reg, alt_u32 w_param){   alt_u32 watchdog = 0x00;  alt_u32 r_param ;   do{  watchdog++;  IOWR(vipBaseAddress, reg, w_param);  r_param = IORD(vipBaseAddress, reg);  }  while( (r_param != w_param) && (watchdog != TIMEOUT) );   return (watchdog == TIMEOUT)?1:0; }  When I try to read the new value I always get 0x0000. What am I doing wrong?  Thx, Lionel.

[Altera_Forum]

I've never used that core before but here are some things to check: 

 1) Make sure 'reg' is a 32-bit word offset. So if the registers are spaced at bytes 0x0, 0x4, 0x8, 0xC, 0x10, etc.... then you use 'reg' offsets of 0, 1, 2, 3, 4, etc... to access them (IORD and IOWR are 32-bit word access macros)   2) Make sure that the register you are accessing is readable, sometimes hardware folks don't bother making their registers read/write capable.

[Altera_Forum]

I've checked the doc and the width of the data of the slave interface is well 32 bits. 

 For the readable of my registers if found this: - Control register : Setting the bit 0 to 0, causes the Scaler II to stop the next time that control information is read. - Status register : When this bit is set to 0, the Scaler II sets this address to 0 between frames. It is set to 1 while the MegaCore function is processing data and cannot be stopped.

[Altera_Forum]

I looked at the doc, so make sure the 'reg' value you are passing in corresponds to the value in the Address column of table 21-8.

[Altera_Forum]

I've defined : 

 #define ALT_VIP_SCALER_II_CONTROL_REG 0# define ALT_VIP_SCALER_II_STATUS_REG 1  and I call my function like this :  ALT_VIP_SCALER_II_GOBIT(ALT_VIP_CL_SCL_LCD_DF_BASE, 0x00);  With ALT_VIP_CL_SCL_LCD_DF_BASE the base address of my scaler given by system.h in the bsp.

[Altera_Forum]

It's possible that the go bit isn't readable and it's expected that you read from the status register to find out if the hardware is stopped. That's just speculation on my part since I don't think the HDL is plain text. I would file a support ticket at www.altera.com/mysupport (http://www.altera.com/mysupport) to get a better description of those registers (and recommend that they improve the documentation)

[Altera_Forum]

Sorry for my mistake, 

 Actually the stop and start work fine with the Scaler Core. My problem is with others registers. This is how I use my function : # define ALT_VIP_SCALER_II_OUTPUT_WIDTH_REG 3  ALT_VIP_SCALER_II_WRDATA (ALT_VIP_CL_SCL_LCD_DF_BASE , ALT_VIP_SCALER_II_OUTPUT_WIDTH_REG , 600 );  Output Width register is a readable and writable register.  Anyway, thank you for your help, I'll follow your advice by opening a ticket. If you have others suggestion, don't hesitate ;)

[Altera_Forum]

I assume that core comes with the Nios II macros you are using to access those registers. If so I would check to see if they have specific macros for each register, it makes things easier because you don't have to worry about register offsets because it's taken care of by the macro itself. Most (or all) of the embedded cores in Qsys have macros such as these. For example these are the macros used to read and write the IRQ mask of the PIO component: 

# define IORD_ALTERA_AVALON_PIO_IRQ_MASK(base) IORD(base, 2) # define IOWR_ALTERA_AVALON_PIO_IRQ_MASK(base, data) IOWR(base, 2, data)   If the Scalar II core doesn't have such macros I would mention in your service request that they should probably be present.