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Using the 3.3V Proto-Card Pins On Nios Board

Altera_Forum
Honored Contributor II
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hi,  

 

I'm using the @ltera Nios Developement Board, with the Apex20K200E FPGA onboard, for SoC design implementations.  

 

Can anyone confirm that for the 3.3V proto-card pins to be used as IO pins for data transfer/input-output, one has to enable the card by connecting a VCC supply to pin_V6 in the Apex20K200E device. This pin, as I have discovered, is to enable use of 3.3V proto pins.  

 

Has anybody else faced the same design challenge...? My doubt is whether a VCC or GND supply has to be connected to this pin.  

 

Thanks.
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3 Replies
Altera_Forum
Honored Contributor II
96 Views

Hey; 

 

You are correct, for the Proto - card connectors JP11 JP12 and JP13 you need to tie pin_V6 low in order to enable the quick switches that the IO connections pass through to the headers. The proto - card connectors JP8 JP9 and JP10 do not require this because they do not have quick switches in between them and the PLD. These Apex boards are the only ones that require that pin to be pulled low. All the boards since then have the quick switches on all the proto - card connectors but they are always active and do not require an enable signal. 

 

Kenyon
Altera_Forum
Honored Contributor II
96 Views

To all: 

 

JP11, 12, 13 "are golbally enabled by APEX device I/O ping v7 " from NIos Embeded processor Development board "DATA SHEET" . So pin V6 is connected to pin38 of JP11 in 5V Expansion and BE# in Switchs . 

 

And pin_V6 is connected to pin38 of JP8 in 3.3V Expansion. 

 

Hi, kkluge, do you agree with me?
Altera_Forum
Honored Contributor II
96 Views

Yep, Sorry for the mistake on the first post. It should read pin_V7 is the quick switch enable pin, not pin_V6. 

pin _V6 is essencial just another IO pin to the connector but with a pull up resistor on it.
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