Hello everyone,I'm working on a project which takes some ADC samples, analyzes them and draws an image to the screen through VGA. So far I designed a VGA controller which takes image from memory buffer, a memory controller to store ADC samples in it and I made some simple rendering in VHDL. However, it would take so much time to design a proper rendering algorithm in VHDL, so I decided to use Nios2 for rendering. I faced many problems during this process and a new one appears - I want to ask you about it. How can I specify a fixed memory region to be used both by VHDL and Nios2? My MAX10 device has 48 384 bytes of memory (however I cannot implement a dual port memory block with size greater than 28 672 bytes - out of M9K), so I have 28 KB of memory. I want to reserve 18 KB for screen buffer and 8 KB for ADC samples, leaving 2 KB free memory for microprocessor (if it's not enough I can leave more) At this moment, using IORD in Nios2 and Avalon-MM interface's write instructions in VHDL I successfully wrote and read data from VHDL to Nios2. But it feels kinda unsafe to put a fixed address into VHDL interface address signal and read it in Nios2 - somehow, someday, something in Nios2 may use this address to store a variable/stack/heap and the program will malfunction. May I ask you for help? Here's my qsys design: http://i.imgur.com/5KwTOmL.png Thanks in advice. Yours, Adrian
If I understand you correctly, all you need to do is create separate memory regions for each function.I'm assuming your ADC sampling can be controlled/read directly by the NIOS and stored in (eg) software FIFO's in normal program data space? This would be accessed from static/global variable space, heap or stack depending on how you choose to write your software. No addressing or contention issues there as the NIOS is pulling samples from the ADC and storing them internally. Then you'd need a dual-port frame buffer in on-chip memory that can be rendered by the NIOS on one port and read by your VGA controller on the other port for display. This memory block is completely distinct from your NIOS program/data memory so you don't have to worry about addressing or contention issues between the NIOS and "VHDL".