Vector sizes for Qsys generated HPS memory pins

[Altera_Forum]

I'm using SoCKit rev C, SD Card image 14.0 from Rocketboards, Quartus II 14.0. 

 All the reference designs I've seen have the following in the Qsys generated port list of the top level soc_system.v :   output wire [14:0] memory_mem_a, // memory.mem_a  output wire [2:0] memory_mem_ba, // .mem_ba  output wire memory_mem_ck, // .mem_ck  output wire memory_mem_ck_n, // .mem_ck_n  output wire memory_mem_cke, // .mem_cke  output wire memory_mem_cs_n, // .mem_cs_n  output wire memory_mem_ras_n, // .mem_ras_n  output wire memory_mem_cas_n, // .mem_cas_n  output wire memory_mem_we_n, // .mem_we_n  output wire memory_mem_reset_n, // .mem_reset_n  inout wire [31:0] memory_mem_dq, // .mem_dq  inout wire [3:0] memory_mem_dqs, // .mem_dqs  inout wire [3:0] memory_mem_dqs_n, // .mem_dqs_n  output wire memory_mem_odt, // .mem_odt  output wire [3:0] memory_mem_dm, // .mem_dm  input wire memory_oct_rzqin,  The above vector sizes correspond to number of pins that connect to the HPS-side DDR3 device on the SoCKit board, as spec'd in the SoCKit User Manual. For example, Sockit has HPS_DDR3_DQ[31:0] connections as the data bus going out to the HPS-side DDR3.  In my design, Qsys generated the following:   output wire [12:0] memory_mem_a, // memory.mem_a  output wire [2:0] memory_mem_ba, // .mem_ba  output wire memory_mem_ck, // .mem_ck  output wire memory_mem_ck_n, // .mem_ck_n  output wire memory_mem_cke, // .mem_cke  output wire memory_mem_cs_n, // .mem_cs_n  output wire memory_mem_ras_n, // .mem_ras_n  output wire memory_mem_cas_n, // .mem_cas_n  output wire memory_mem_we_n, // .mem_we_n  output wire memory_mem_reset_n, // .mem_reset_n  inout wire [7:0] memory_mem_dq, // .mem_dq  inout wire memory_mem_dqs, // .mem_dqs  inout wire memory_mem_dqs_n, // .mem_dqs_n  output wire memory_mem_odt, // .mem_odt  output wire memory_mem_dm, // .mem_dm  input wire memory_oct_rzqin, // .oct_rzqin  Question: What would make my Qsys generated vector sizes different from every other design I've seen?

[Altera_Forum]

Looks like you setup the memory to be only 8-bits wide and have two fewer row address bits than the design at the top uses. That means the span of the memory you setup is 16 times less than the one at the top.