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Valued Contributor III
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Vectored Interrupt Controller VIC Respond if i take out Ethernet Connector RJ-45

Hello Friends 

 

I am getting Continuous interrupt on nios-II, and this interrupt handle by VIC (Collected by edge_capture register-Please see attached jpeg ). 

 

whenever interrupt come i assert HIGH to nios-ii External pin Temp_out. 

 

but VIC not able to handle all the interrupt and stuck in between or before collecting all the interrupts (Please see attached jpeg). 

 

but if i take out ethernet port rj-45 from my ESDK-Cyclone-III board , vic collect all the interrupt

 

what measure should i take for vic to collect all the interrupt...? 

 

Regards 

 

Kaushal
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Valued Contributor III
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--- Quote Start ---  

Hello Friends 

 

I am getting Continuous interrupt on nios-II, and this interrupt handle by VIC (Collected by edge_capture register-Please see attached jpeg ). 

 

whenever interrupt come i assert HIGH to nios-ii External pin Temp_out. 

 

but VIC not able to handle all the interrupt and stuck in between or before collecting all the interrupts (Please see attached jpeg). 

 

but if i take out ethernet port rj-45 from my ESDK-Cyclone-III board , vic collect all the interrupt

 

what measure should i take for vic to collect all the interrupt...? 

 

Regards 

 

Kaushal 

--- Quote End ---  

 

 

Hi, 

 

How are your settings for the VIC driver in your BSP? 

Are you using MicroC/OS-II ? 

 

regards
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Valued Contributor III
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Hello meds7, 

 

Thanks for reply. 

 

yes i am using MicroC/OS-II and attached (in previous post) is my SOPC file which show my VIC setting. here i connect  

VIC interrupt_controller_out to CPU interrupt _controller_in &  

CPU data_masetr to VIC csr_access, 

 

kaushal
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Valued Contributor III
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if i change the clocking scheme of project in SOPC, VIC start receiving all the interrupt. 

 

if i assign clock to ddr2_bot_auxfull insted of ddr2_bot_auxhalf VIC start collecting all the interrupt. 

 

but at the same time other peripheral like UART stop working. 

 

please put light on clocking arrangement for VIC and other peripheral to work properly
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Highlighted
Valued Contributor III
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--- Quote Start ---  

if i change the clocking scheme of project in SOPC, VIC start receiving all the interrupt. 

 

if i assign clock to ddr2_bot_auxfull insted of ddr2_bot_auxhalf VIC start collecting all the interrupt. 

 

but at the same time other peripheral like UART stop working. 

 

please put light on clocking arrangement for VIC and other peripheral to work properly 

--- Quote End ---  

Hi Kausal, 

I think that your original clocking method should be ok (although it is hard to see with a collapsed view of your SOPC design) but maybe you are facing problems with timing. 

What speed do you use for your DDR controller. What speed is tha half clock? Does your design meet all timing constraints? 

Although that you first must be sure that there is no hardware issue, I want to inform you that I have some doubts that the external VIC is working correctly. 

The VIC is highly configurable with the BSP driver settings. Look into your BSP, go to driver tab and see all the checkboxes that you can enable/disable for preemption of the interrupts. 

I asked Altera about details and they told me that if all these preemption checkboxes are disabled that the VIC should behave on a first come first served base. This should then be the same behaviour as the default internal IIC. 

The strange thing however is that I tested both implementations with my current design and same MicroC/OS-II based software and that the IIC implementation works correct but the VIC implementation results in unsuspected behaviour. 

To my opinion this is strange because behaviour should be the same. 

Maybe you can also test in your situation if the internal interrupt controller leads to better results. I am very curious about that in your case. 

So far I have been searching in this forum to any topics about the VIC and it is very weird that everybody talks about similar weird behaviour and also that nobody responds to working solutions. 

I am beginning to doubt if this IP block is thoroughly tested.....or at least come to the conclusion that this IP block is not well explained and or supported with good reference designs. 

regards
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Valued Contributor III
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By the way, are you using Qsys or SOPC? I know that there have been stupid issues with the VIC when Altera started porting to Qsys but with the latest release it seems to me that all these issues have been solved. I am using 13.0 and Qsys only. Not knowing what other issues are left now :(

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Valued Contributor III
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Thanking you for your post 

1. I am using SOPC 

2. ddr2_bot_auxfull = 165.0 Mhz 

3. ddr2_bot_auxfull = 165.0 Mhz 

4. ddr2_bot_auxhalf = 82.5 

5. I haven’t give any time constraints though Quartus generate message like critical warning: timing requirement not met 

 

6. I just modified the simple socket server example for my requirement like taking data on every interrupt from external pin of nios and store it and also acknowledge received interrupt on external pin temp_out 

 

7. Regarding preemption I haven’t any knowledge but I think this can be use when multiple interrupt use same shadow register. 

8. I have 7 shadow register set and VIC can handle 9 interrupt 

 

regards 

 

Kaushal
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Valued Contributor III
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--- Quote Start ---  

Thanking you for your post 

1. I am using SOPC 

2. ddr2_bot_auxfull = 165.0 Mhz 

3. ddr2_bot_auxfull = 165.0 Mhz 

4. ddr2_bot_auxhalf = 82.5 

5. I haven’t give any time constraints though Quartus generate message like critical warning: timing requirement not met 

 

6. I just modified the simple socket server example for my requirement like taking data on every interrupt from external pin of nios and store it and also acknowledge received interrupt on external pin temp_out 

 

7. Regarding preemption I haven’t any knowledge but I think this can be use when multiple interrupt use same shadow register. 

8. I have 7 shadow register set and VIC can handle 9 interrupt 

 

regards 

 

Kaushal 

--- Quote End ---  

 

 

Hi, 

I would highly recommend you to first get your hardware design correct with proper timing constraints. 

If not then you cannot be sure what the origin of your problems could be.  

If you do not have any understanding or knowledge about interrupt preemption then I would also recommend you to switch back to the internal IIC. 

I mean; what is your reason that you have chosen to use the VIC instead of the IIC? 

regards
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Valued Contributor III
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The Hardware which i am using is provided by Altera, and code which i am using is modified version of simple_socket_server example,  

 

i have add only sync_detector which extract synchronous word from serial bit stream and start generating load pulse at every 8-bit (conversion time from serial to 8 bit parallel data). so that at every pulse this 8-bot data to be read and store in FPGA memory 

 

as this load pulse (interrupt ) comes at every 125 kbps which IIC not able to handle (it misses most of the interrupt) so i switch to VIC. 

 

in my previous project i am comfortable use the VIC and have not face any problem like this. 

 

I am using altera ESDK board (Cyclone-III)  

my application is like this 

 

 

Image data (TCP) PC---->ESDK-RX---------Serial Synchrionous Data @ 1 mbps------>(Sync Detect)-->ESDK-Tx------>PC (Received Image Data through TCP) 

|-------------------------------Project-I----------------------------->|<----------------------Project-II------------------------->| 

 

 

Rather i am using my previous project hardware for development of new project 

 

 

 

Regards
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