Hey<br><br>I'm struggling to overcome a verification errors when attempting to download my .elf onto my Cyclone 4 E. I can get the "hello world" example to download when only using onchip mem but cannot when an sdram module is present. Even if the nios core references only onchip mem, if the sdram module is connected to the data/instruction buses then it isn't able to verify the program I try to download. I believe this to be caused by the base addressing scheme but do not understand it well enough to validate my theory. I've always used the "assign base addresses" tool in Qsys but this has not helped. I've also used the base addressing scheme as assigned when only onchip mem is present and an sdram module added after. Still this has not worked and strangely nios attempts to read from 0x80000000 onward despite onchip mem begining at a smaller address. <br><br>I don't think the memory chip itself is at fault as even when the nios core is meant to be using onchip mem the nios ide reports that 0x8000000 to 0x8000XXXX is being scanned. Not sure really what to do about this as I've spent a couple days trying to debug these problems with no luck. Please help! <br><br><br>Using the base addressing scheme as per the onchip mem config with the nios core referencing onchip mem:<br><img src="http://www.alteraforum.com/forum/attachment.php?attachmentid=10295&stc=1" attachmentid="10295" alt="" id="vbattach_10295" class="previewthumb"><br> <br>Problem itself<br><img src="http://www.alteraforum.com/forum/attachment.php?attachmentid=10296&stc=1" attachmentid="10296" alt="" id="vbattach_10296" class="previewthumb">
Is this DE0-Nano? I have seen timing issues reported where Nios unable to access the SDRAM due to clock skew issue. It is recommended to generate a 3ns clock that leads Nios clock to the SDRAM controller.Reference: ftp://ftp.altera.com/up/pub/altera_material/11.1/tutorials/verilog/de0-nano/using_the_sdram.pdf, section 7. Hope this helps.