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12408 Discussions

Verifiy failed between adr.... in SRAM DE2-115 tPad Simple Socket Project

Honored Contributor I

Hi There, 


I try to build the SimpleSocketServer_rgmii_0 on my DE2-115 tPad. 

I could generate the System in SopC and Quartus successfull but in Nios 

I became this error message: 


Using cable "USB-Blaster [USB-0]", device 1, instance 0x00 

Pausing target processor: OK 

Reading System ID at address 0x014034E0: verified 

Initializing CPU cache (if present) 



Downloading 01200000 ( 0%) 

Downloading 01210000 (20%) 

Downloading 01220000 (41%) 

Downloading 01230000 (61%) 

Downloading 01240000 (82%) 

Downloaded 313KB in 5.3s (59.0KB/s) 


Verifying 01200000 ( 0%) 

Verify failed between address 0x1200000 and 0x120FFFF 

Leaving target processor paused 




In the System Lib Properties i set the Prog memory and the rest all of sram. 

In SopC I use the SRAM-Controller from the University Program IP. I try also the IP from TERASIC --> TERASIC_SRAM, still with both version the same error. 


I run also the Standalone Quartus Prog for program the sof file and then I leave the unlimited window open. I thing that are not the problem. 




Please help me to find a solution  


Thanks you 

0 Kudos
2 Replies
Honored Contributor I

in the attachment you find my SoPc System. 


In NiosII I use the template simple_socket_server_rgmii_0 



Honored Contributor I

Had a similar problem with Terasic SRAM when it is connected to a NIOS II/f (NIOS II/e - no problem). This is because the II/f is much faster (can have transactions one after the other due to the pipeline that it has). I solved this by modifying the Terasic SRAM component in the SOPC system by adding having 2 read waitstates, 2 write waitstates, and 1 hold cycle and 1 setup cycle (this is probably an overkill, you could probably omit a few of the wait states or setup/hold cycles). Now it works without a problem with the II/f (NIOS CLK = 50 MHz). I recommend using the SDRAM for the NIOS, because it is faster and has more capacity than the Terasic SRAM. If you must use the SRAM, change the SOPC component as I indicated above.