Nios® V/II Embedded Design Suite (EDS)
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Verify failed between address 0x4011800 and 0x401181F

Altera_Forum
Honored Contributor II
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I have this error on my two project without I had change nothing! 

Exact same error, but not same card!? (Bemicro and DE0-Nano) 

 

The only change I can find, it's the end of my subscription. I don't have update anything. Juste recompile and upload the Sof and the Nios.Please help!!
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Altera_Forum
Honored Contributor II
519 Views

What device has been mapped at that address range?

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Altera_Forum
Honored Contributor II
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Since that is a 32 byte address range, and the jtag loader only reports the entire range (not where it got the first error), I suspect that is one of the interrupt vector/rest locations.

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Altera_Forum
Honored Contributor II
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It's the  

reset 0x04011800 - 0x0401181F epcs_flash_controller 32 0 

 

But I didn't change anything on both project. So why it's stop working?
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Altera_Forum
Honored Contributor II
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And I checked the EPCS with the Terasic control panel

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Altera_Forum
Honored Contributor II
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If the reset vector is inside the epcs_flash_controller, I don't think your program image should have any code for that address. 

Something will have gone wrong inside all the 'magic' that attempts to make building a loadable image easy. 

The images I build are so dissimilar from those the IDE generates I couldn't even comtempate beating it into submission. 

Not only that, we download the code from system filestore - so the system used to compile to code doesn't need any of the Altera software installed - just gcc for nios2.
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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

It's the  

reset 0x04011800 - 0x0401181F epcs_flash_controller 32 0 

 

--- Quote End ---  

 

This is the nios bootloader address (I thought this was excluded from verification, but probably I was wrong). 

Do you use a standard bootloader? Check if you changed the epcs_controller_boot_rom.hex file in the Quartus project. You can regenerate the file by rebuilding the Qsys module.
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