Hi everyone,i know this subject has been discussed a lot of times, but i don't find any solution for my case. I 'm working on a DE2 115 board trying to get a TCP stack on uCos. As usual, i do my SoC with a nios 2 and so on... But when i tried to download the .elf to the system i got this great message that tells me "failed to download .elf" and a "verify failed between address x80000 and ...".https://www.alteraforum.com/forum/attachment.php?attachmentid=8405 This address range corresponds to my main memory. So, i did a very simple design with a nios2, jtag uart and mem of 65536 Bytes, just to see the behavior, and guess what? it doesn't work neither and tells me the same message. I did a project 6 months ago with 11.1 version of Quartus and i never encountered this problem. Since i installed the new 13.1 version a week ago, i got this message on all my old designs. Is it possible that 13.1 hates me? I never cheated it, or maybe one time. This was a night, MicroSemi just told me how beautiful i was, and i... No, i just don't want to remember. If someone has the solution, i take it. Thank you.
Quartus 10 and 11 seem to be avoided because they are the transitions from SOPC to QSYS.How did you make your simple design ? from scratch or from templates ? common causes are : reset signal, watchdog... timings of mem wrong Qsys found (if you don't have sysid...) are ignored sysid/timestamp Have you tried with an other board ?
Thanks for your replyIs the sysid IP from Qsys mandatory? and yes, i tried on another de2 115 board. You're right, i should try it on my other cyclone3 board.
Hi again,problem was solved by deleting inverter on KEY(0) which was used for reset. I just want to die... so confused Thank you mmTsuchi for your advices. Have a nice week end