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Altera_Forum
Honored Contributor I
761 Views

Verilog - minimizing logic

Hi 

 

I'm generating some asymmetric waveforms from a counter, and am able to adjust the counts where it changes output. Hence I'd like to choose numbers that utilize the minimum amount of logic - e.g: 

 

Counter8_out = ((Counter1 >= 48) && (Counter1 < 80)) | 

((Counter1 >= 128) && (Counter1 < 176)) | 

((Counter1 >= 208) && (Counter1 < 256)) | 

(Counter1 >= 304); 

 

Is there any way I can see what effect tweaking the numbers has on the compiled logic, e.g. seeing how much logic is used by that signal, or seeing the canonical equation produced by the synthesis (IIRC there was a way of seeing that from MAX-PLUS-II)? 

 

[edit] - other than by compile, print-screen "resource usage summary", tweak, compile, compare "resource usage summary" against previous... 

 

[edit] - also seeing that adjusting the counts to use a spread of 2,3,4 input Logic Element usage can work better than trying to always use minimum number of bits.
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Altera_Forum
Honored Contributor I
36 Views

This kind of compare logic is minimized if you choose numbers which allow comparision of a limited number of bits. 

This can be easily evaluated from the binary representation of you numbers, 

e.g (Counter1 >= 128) && (Counter1 < 176) is efficient because only 3 upper bits need to be compared in order to evaluate the expression. 

While (Counter1 >= 135) && (Counter1 < 182) would require far more complex logic.
Altera_Forum
Honored Contributor I
36 Views

ISTR that somewhere you can see a logic diagram (or similar) after one stage of the syntheses. But the actual logic used can depend on timing (and other) constraints. 

 

I'd guess that you'd be better counting down to zero (or until carry) and reloading the counter with a sequence of values.
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