Hi everybody.I am loosing my mind with this issue... I have made a FFT of 256 point, in c code, that runs very fast in my pc. The code calculates FFT points and prints them in screen. So every time i can see the new pair of numbers. When i using the same code in Eclipse the process is very slow. I see a new pair of numbers in about every half of a second, with the Media Computer from University Program. when i use the same code at a microcontroller (eg pic at 2 mhz) the results are extremly fastest than my fpga at 50mhz !!!!! I have try to solve this, with different optimizations of compiler (-O3) and using the nios II/f combinations, spending a lot of days, but no luck. I believe that the code is running in a debug mode, or somehow eclipse spent some time to communicate with my board. Is there a way (manual or tutorial) to put my code in FPGA as like i do with my microcontroller ? Because i am new in NIOS II, i am confused with all Altera's manuals and i wonder if someone can make me a suggestion. I use DE2-115 board and quartus 11.0 at Win7. Best Regards Chris
Hi there,so you calculate the FFT in the NIOS and transfer it to the media computer by what? Does your sample code use float? You could add the Performance counter and measure how long parts of your application take: http://www.altera.com/literature/an/an391.pdf Page 13 Or any of the other profiling methods from this document to try finding the bottle neck Good luck
Are you doing the FFT using double, float or integer (fixed point) data types.Unless you are using integers it will be slow, even more so if you are using soft-float. The soft-float code will be even worse if the BSP (which contains the FP functions) hasn't been compiled with -O3. You can do fast (integer) FFT on a DSP - by throwing dedicated hardware at it. Your PC could be running a 3.5GHz, your nios probably at no more than 100MHz. The PC can execute several instructions every clock, the nios at most one. The PC will have enough instruction and data cache to hold all the code and data in cache, the nios migh have enough instruction cache, but is probably thrashing the data cache. The PC can do an FP multiply of divide every clock (more if your code is using any of the SIMD instructions - which FFT could generate). All in all, I wouldn't be surprised if the nios code is 1000 (or more) times slower.