WISHBONE AVALON BRIDGE - migration problem ?

[Altera_Forum]

Hello, 

 in former times I used Quartus v9.1 and NIOSII v.9.1 with an Cyclone II FPGA. Actual I use Quartus v10.1 and NIOSII v.10.1 with an Cyclone IV FPGA.  Since I changed both (devleopment software and FPGA), the WISHBONE-AVALON BRIDGE does not work. In the follwing code, there is VHDL File for mapping the BUS Signals and the TCL file for creating the component in SOPC Builder.  The problem I have is, that NIOS write no valid adresses. In the memory table there are false data.  I did not change all code which deals with the WISHBONE AVALON BRIDGE.  Has anybody an idea what the reason for it can be?  # #################################### ################################### VHDL - BRIDGE WISHBONE-AVALON# #################################### ################################### ....   WB_ADR <= AV_ADR;  WB_CYC_IN <= AV_CS;  WB_STB_IN <= not AV_WE_N or not AV_RD_N;  WB_WE_IN <= not AV_WE_N and AV_RD_N;  AV_WAITREQ <= not WB_ACK_O;    WB_DAT_O <= AV_DAT_IN;   process(AV_BYTE_EN)  begin  AV_DAT_O <= WB_DAT_IN;  end process; ....  # #################################### ################################### TCL FILE - Component in SOPC Builder# #################################### ################################### # +-----------------------------------# | connection point avalon_slave_0# | add_interface avalon_slave_0 avalon end set_interface_property avalon_slave_0 addressAlignment DYNAMIC set_interface_property avalon_slave_0 addressUnits WORDS set_interface_property avalon_slave_0 associatedClock clock_sink set_interface_property avalon_slave_0 associatedReset clock_sink_reset set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false set_interface_property avalon_slave_0 explicitAddressSpan 0 set_interface_property avalon_slave_0 holdTime 0 set_interface_property avalon_slave_0 isMemoryDevice false set_interface_property avalon_slave_0 isNonVolatileStorage false set_interface_property avalon_slave_0 linewrapBursts false set_interface_property avalon_slave_0 maximumPendingReadTransactions 0 set_interface_property avalon_slave_0 printableDevice false set_interface_property avalon_slave_0 readLatency 0 set_interface_property avalon_slave_0 readWaitTime 1 set_interface_property avalon_slave_0 setupTime 0 set_interface_property avalon_slave_0 timingUnits Cycles set_interface_property avalon_slave_0 writeWaitTime 0  set_interface_property avalon_slave_0 ENABLED true  add_interface_port avalon_slave_0 AV_WE_N write_n Input 1 add_interface_port avalon_slave_0 AV_RD_N read_n Input 1 add_interface_port avalon_slave_0 AV_WAITREQ waitrequest Output 1 add_interface_port avalon_slave_0 AV_BYTE_EN byteenable Input 4 add_interface_port avalon_slave_0 AV_ADR address Input 16 add_interface_port avalon_slave_0 AV_DAT_IN writedata Input 32 add_interface_port avalon_slave_0 AV_DAT_O readdata Output 32 add_interface_port avalon_slave_0 AV_CS chipselect Input 1# |# +----------------------------------- # +-----------------------------------# | connection point clock_sink# | add_interface clock_sink clock end set_interface_property clock_sink clockRate 0  set_interface_property clock_sink ENABLED true  add_interface_port clock_sink CLK clk Input 1# |# +----------------------------------- # +-----------------------------------# | connection point conduit_end# | add_interface conduit_end conduit end  set_interface_property conduit_end ENABLED true  add_interface_port conduit_end WB_WE_IN export Output 1 add_interface_port conduit_end WB_STB_IN export Output 1 add_interface_port conduit_end WB_CYC_IN export Output 1 add_interface_port conduit_end WB_DAT_IN export Input 32 add_interface_port conduit_end WB_DAT_O export Output 32 add_interface_port conduit_end WB_ACK_O export Input 1 add_interface_port conduit_end WB_ADR export Output 16# |# +-----------------------------------   THANK YOU

[Altera_Forum]

It might be the chip select, I have been hearing about problems with that signal lately. If you need a chip select for Wishbone, just 'OR' the read and write signals together which would eliminate the need for the chip select wire on the Avalon side.

[Altera_Forum]

Hi BadOmen, 

 thank you for your reply. I try to combine the chip select with the read and write signal (OR) and it works so far. :D  In an other case, i use the wishbone-avalon bridge to communicate with an Ethercat modul (Hilscher COMX). In this application, it does not work. :(  I have tried to look on the handshake signals, but i have seen no activity on this signals.   Can there be at this point a further problem?  Thank you

[Altera_Forum]

By handshake signals do you mean read, write, byte enable, etc...? If you are not seeing those transition I would guess it's one of two things: 

 1) the wiring in the bridge isn't connected and transactions are being lost (doubtful if this worked before)   2) accesses to the bridge are not reaching the slave port and as a result nothing comes out the other side.   If you haven't already done so I would simulate the system so that you can get the big picture of what is going on. Alteratively you could signaltap both sides of the bridge and the master accessing the bridge. You don't need to capture all the signals, probably address, read, and write would be a good set of signals to look at to see if transactions are being lost. If you see something suspect then you can add data to get a better idea what's going on.