We are using Arria10 FPGA to implement our custom IP controller. The controller has both AHB slave as well as AXI master interfaces. The controller's registers are accessed using NIOS II Processor via AHB slave interface. The AXI master interface is connected to the the on-chip memory which is accessed by NIOS II processor also. We are not getting proper data when we do a read access to the on-chip memory via the AXI interface. Could you pl. suggest how to debug this?
Thanks for your screenshot attached,
can you remove the AXI interface first and check on the signal tap? This will help to narrow down whether the problem is coming from the AXI.
Our controller has both AHB slave as well as AXI Master interface. So the bridge component that we created in the QSYS system has both AHB and AXI interfaces.
AHB interface is used to access our Controller’s internal registers from NIOS II processor. AXI interface is used to access the on-chip memory from our controller
AHB interface works fine, we are able to read/write to our Controller’s internal registers from NIOS II processor. The issue is seen with AXI interface, when we do a read access to on-chip memory from our controller, we are not getting back the data properly.
So removing the bridge will not help in our testing. Do you have any other suggestion on how to connect the AXI interface form our controller to the Avalon interface of the on-chip memory?
The bridge that you are using uses AHB, which means there are 3 conversion happening avalon -> AHB -> axi
Are you sure you using the correct bridge?
As mention, can you remove the bridge temporally to make the test so that we can Isolate those issue are comming out from the bridge.
I've captured the system connectivity details between NIOS II CPU and our Custom IP controller in the attached diagram. Could you pl. check and let us know if anything needs to be corrected?
I can see that your axi slave is exported out from the qsys. Which means your controller is a standalone design? Can you try to make your controller to put in the qsys design?
The reason to do that is to let the qsys to decide whether addition adapter need to be added. By exporting out the interface, qsys will not be identify what is happening outside.