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Hi,
We are using Arria10 FPGA to implement our custom IP controller. The controller has both AHB slave as well as AXI master interfaces. The controller's registers are accessed using NIOS II Processor via AHB slave interface. The AXI master interface is connected to the the on-chip memory which is accessed by NIOS II processor also. We are not getting proper data when we do a read access to the on-chip memory via the AXI interface. Could you pl. suggest how to debug this?
thanks,
sunil
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Hi,
Thanks, will go through the youtube video.
But to connect NIOS II CPU & On-chip memory with our standalone controller design, we created one bridge component in QSYS. Pl. refer to the attached diagram. Will this not work?
Rgds,
sunil
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It should be fine, what you need to check is the interconnect whether it is make sense.
You can refer to https://www.youtube.com/watch?v=LdD2B1x-5vo
It teaches you how to check the interconnect.
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Hi,
I went through both the youtube videos. As per the first video only, we had created a bridge component and instantiated in the QSYS design.
The second video talks about the interconnect components being used. I did check the same in our design, could see various components being used to convert from Avalon to AHB as well as Avalon to AXI interfaces. I’m not sure what to check exactly in this as I am not familiar with these interconnect components. Is there anything specific I need to check?
Rgds,
sunil
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