You can run Nios II RTL simulation to verify your design without downloading to FPGA.
Platform Designer will allow you to generate a testbench and a tcl file for simulation using ModelSim. Nios SBT will allow you to generate .mif files (your C code) for memory initialization.
You may refer to page 433 to 439 of below:
The method or link I listed below will work for Nios simulation (with application C code).
Do you have anymore question ? can we close the case ?