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We use in the lab Altera Monitor Program to download the NIOSII Processor on the FPGA chip and to compile the C-language codes. is there any way or simulator to do the experiments during lockdown without the Chip?

 
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Hi, Zabin


You can run Nios II RTL simulation to verify your design without downloading to FPGA.


Platform Designer will allow you to generate a testbench and a tcl file for simulation using ModelSim. Nios SBT will allow you to generate .mif files (your C code) for memory initialization.


You may refer to page 433 to 439 of below:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/nios2/edh_ed_handbook.pd...


https://www.intel.com/content/www/us/en/programmable/support/support-resources/design-examples/intel...


Thanks.


Eric




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Hi, Zabin


The method or link I listed below will work for Nios simulation (with application C code).


Do you have anymore question ? can we close the case ?


Thanks.


Eric