Hi, I am new on using Qsys. In Qsys, it provided us to either create simulation model or create testbench system. Both of them are used for simulation like in Modelsim, right?Anyone know the different between the create simulation model and create testbench system? I wish to run simulation on modelsim. http://www.alteraforum.com/forum/attachment.php?attachmentid=11607&stc=1 http://www.alteraforum.com/forum/attachment.php?attachmentid=11608&stc=1
If you select create simulation model, Qsys will generate the simulation friendly RTL only and you will need to write your own testbench with clocks and resets.If you select create testbench system, Qsys will generate simulation friendly RTL plus a testbench wrapper that instantiate your Qsys system and BFMs for clocks and resets. It will produce 4 folders: mentor, aldec, cadence and synopsys each for different simulators.
Thanks Mikedsouz.Does it mean that if I select create testbench system, it can help me to ease my job from writting own testbench? Also, what is the function of the BFMs for clock and reset in this case?
It should help you but do note that the testbench is a fairly simple one with clock and reset. You can expand the testbench by adding your own test IP/BFM if you need to test more than just the clock and reset.The BFM for clock and reset are basically simple clock and reset generator, nothing fancy with these BFMs.
The simulation model is exactly this - a model of a given block so that it can be used in simulation. The testbench is just a testbench for the top level (that wont work unless you have the source or sim model for each block). Some IP is encrypted or not available as source, so simulation is not possible without a simulation model.
Thanks all.But I kind of confuse on this BFM simulation example https://www.altera.com/support/support-resources/design-examples/design-software/qsys/exm-hps-axi-bf... From what I know, in Qsys, if we choose to create testbench system option, then Qsys will create testbench system and connects the exported top-level interfaces from your system to Bus Function Models (BFMs). In this design, the exported surfaces is just the clock and reset. Hence, the top level testbench system will instantiate with clock and reset BFM. But, may i know how the HPS BFM model is included in the top level testbench since it does not exported to the top level interfaces in Qsys and Qsys will not instantiate the HPS BFM to the testbench.