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What is the best way to establish a bi-directional high speed communication link between NIOS (eclipse) and the FPGA (VHDL)?




Let's say I've implemented an Ethernet interface on the NIOS platform (to off chip component, Eclipse) and now I want to transfer those data to the FPGA section (VHDL) -and vice versa. What would be the best way to implement such interface? What would be the max transfer rate?    

Thanks a lot,


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The best way to transfer data between Nios II and other peripherals wold be the use of DMA. For example, you can use the mSGDMA soft-core IP. More information can be found here:


Furthermore, you can refer to this video on how to use this IP:


regarding the max transfer rate, this would depend on the operation frequency and the transfer rate of the DMA plus the memory latency. The max transfer rate of mSGDMA would be 2GB, however, this is a theoretical number, and will be affected by the parameters mentioned above.


You can find an example showing how to use this IP, with a software code to test it.





Hope this might help