I am working on a DE0-Nano-SoC kit from Terasic, based on a Cyclone V. In several of the the GHRD and examples the following construct is used:
wire hps_reset_req; hps_reset hps_reset_inst ( .source_clk (fpga_clk1_50), .source (hps_reset_req) );then each of the three bits are fed into 3 altera_edge_detector and then fed into the *_reset_req_reset_n ports in the HPS. What is the function of hps_reset? I can't find any useful docs for this (could not find it in the Cyclone V handbook, in the Quartus II handbooks nor on Alteras website).
All this is a path to let you send reset signals from Quartus II or from Tcl scripts to the HPS (ARM SoC).
hps_reset is a function that Terasic or somebody generated using the (now-obsolete) Megafunction Wizard. You can see its definition (alongside debounce and edge_detect) in ip/altsource_probe/hps_reset.v ; it's just an instantiation of an altsource_probe. Of course, now you need to know what altsource_probe is.
altsource_probe is a device that interacts with the In-System Sources and Probes (ISSP) function, which is a debugging function that lets you read or write lines from Quartus II or the System Console. In this case, it lets you use the ISSP tool to set the "hps_reset" signals. (They show up as RST in ISSP.)
The "hps_reset" signals are then passed through edge detectors. An edge detector means that when one of the lines in the hps_reset signal goes from low to high, the edge detector will keep the associated output (pulse_*_reset) high for several cycles (2-32, depending on which signal; see PULSE_EXT) longer than the corresponding hps_reset signal was high. This is presumably because the HPS needs a certain minimum duration of reset signals.
Finally, these extended signals are sent into the HPS's reset request lines (e.g., hps_0_f2h_cold_reset_req_reset_n). This tells the HPS to reset. There are three different reset signals, which is why hps_reset_req (the output of hps_reset) is three bits wide.
The different types of reset signals are discussed in the Cyclone V Device Handbook, Volume 3: Hard Processor Technical Reference Manual (https://documentation.altera.com/#/link/sfo1410143707420/sfo1410067598309), in the "Reset Manager" chapter.