What's the difference between an Avalon MM Master and an Avalon MM Slave

[Altera_Forum]

I need to design an Avalon MM IP component that allows software running on the HPS of a Cyclone V FPGA to access an external comms chip and an SRAM chip. The comms chip has a memory mapped register set accessed via standard read/write cycles (as does the SRAM obviously) so I just need to handle requests from the software to read to or write from the comms chip or the SRAM. 

 The problem is that I'm not sure if this IP component should be an Avalon MM Master or an Avalon MM Slave (or contain both functions?) because I haven't found any information that tells me what the difference is between an Avalon MM Master and an Avalon MM Slave. Could anyone advise me on what the difference is, what Avalon MM Masters would typically be used for, and what Avalon MM Slaves would typically be used for please. Any other advice would be gratefully received!

[Altera_Forum]

A processor or DMA implements Avalon-MM Master interfaces. 

 A UART or GPIO peripheral implements Avalon-MM Slave interfaces.  A master generates bus requests, while a slave receives those requests.  You would want to implement an Avalon-MM Slave interface.   Also, look into the bundled Tri-State bridge component.

[Altera_Forum]

Thanks for that Ted, it's very useful. I'll start designing my Avalon MM Slave component.

[Altera_Forum]

The ghrd for the Altera Cyclone V has two JTAG to Avalon Master Bridges, hps_only_master and fpga_only_master. As far as I can see these allow you to test the board using system console via the JTAG interface for board bring-up and testing - is this correct? If so, our production board can't include this function as it runs a safety critical application. 

 My question is, when I've implemented my custom avalon memory-mapped interface component, how do I connect it in Qsys to allow the HPS to access it? What mechanism does the HPS use to communicate with slaves if we don't have a JTAG to Avalon Master Bridge?