Hi there,I’m aware that the common design flow when developing FPGA-based systems is to firstly define a HW platform ( e.g. Quartus2 + Qsys + PinPlanner ) and afterwards to make SW project ( e.g. Nios2 ) to run it within. The Altera’s set of software examples shown in the “nios ii application and bsp from template” panel are very useful. However I’ve noticed that they do not provide the .sopcinfo files where these examples are supposed to run. In fact, I could try to make myself at Qsys, but some of these examples are somewhat more complex. In order to go flawless I would like to know which components in library functions are required to place, as well as which ones have to be interconnect to where. The short text at the TextBox mentions that document files are available at nios2eds folder, but I can find just Software, anything of hardware. Does somebody knows if these files are normaly provided by Altera ?
I got the answer, just an update:At the webpage design examples (https://www.altera.com/support/support-resources/design-examples.html) I could find the implementation of the example https://www.altera.com/support/support-resources/design-examples/intellectual-property/embedded/nios... (t;)"]Board Diagnostic[/URL] that I was interested. However, unfortunately it is not free, but available just under the 30 days trial license. Apparently I have to build the interconnections by myself. :cry: