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Altera_Forum
Honored Contributor I
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Why do I need on-chip fifo memory core for buffering?

Hi,  

 

I have an issue where the rate the data is sent to serial port (50Hz) is way faster than the serial port can receive (8Hz).  

 

Basically, what I have is, data is sent from fpga vhdl block to NIos II system, Nios II system sends the data to serial port, Matlab access the serial port to real time plot the graph. 

 

So, I wanted to go for the buffering approach. I am using Quartus 12.1 sp1, vhdl and Nios II programmed in C code for DE0-Nano. In Qsys, I am using a few cores such as timer, sdram, uart, pios etc. 

 

I am totally new to buffering and its hardware interface... I have a few questions: 

 

1. May I know why do I need to use on-chip fifo memory core for this purpose? Can't we just buffer the data in SDRAM? Forgive this newbie question 

 

2.Can we combine both uart ip core with fifo core, or do you mean they are to be done separately? 

 

3. I am confused whether I should use an avalon fifoed uart or any fifo will do? I know there is on-chip fifo memory in Qsys, i am using SDRAM in my system 

 

 

4. I could not find design examples that use fifo, mind to share the link? 

 

Appreciate your time, thank you very much.
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