Hi all,I'm new to the Nios/Qsys/Eclipse. I've used Quartus software before but never with Nios. I'm using a Nios Gen2 with a MAX10 (BeMicroMAX10). The free version of Nios. The base address of the PIO is for the data. Then there is outset and outclear. That's 3 locations. So how come Qsys shows an address span of 16? Thanks
Have a look at the documentation for the pio core (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_embedded_ip.pdf), chapter 11. Depending on the options, a PIO core uses 4 or 6 32-bit registers. In addition to the pin accesses and direction control, you have a edge capture register and an interrupt mask register.
In one case there are 6 x 32bit registers. So that means in powers of two there are 8 x 32bit = 32 bytes.But if you have don't have the extended registers enabled, then there are 3 x 32bit registers - as powers of two that is 4 x 32bit = 16 bytes. Address spans are shown in bytes (even if you are using Word Addressing).
I think the minimum width is 16 bytes.You should also make your slave 32bits wide - return 0 to reads for the top 24 bits. The Nios acceses are 32bit (with appropriate byte enables for writes) and logic gets added to generate 4 cycles to an 8bit slave.
--- Quote Start --- You should also make your slave 32bits wide - return 0 to reads for the top 24 bits. The Nios acceses are 32bit (with appropriate byte enables for writes) and logic gets added to generate 4 cycles to an 8bit slave. --- Quote End --- Do You suggest to make all PIO registers ( connected to NIOS II as slaves in QSys ) 32-bits wide even though only several bits are used? What C type variable should then be used? Apparently, unsigned int ?