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Altera_Forum
Honored Contributor I
1,226 Views

Why my Nios II run slowly ?

Dear all, 

 

I have do experiment on the Cyclone V SOC. [Helio evaluation board] 

And I put one nios/e and onchip-ram into the FPGA fabric. 

Currently, I could read/write the data in/out from Onchip RAM. 

 

Now, I am measuring the time duration for my source code. 

I discover that each instruction runs slowly. 

 

Below is my simple source code. 

 

I don't understand that the one line[*pdata = i++;] I comment , it needs to take 1us

It should not be correct performance. 

Or should I choose the better version of Nios II ? 

 

Anyone could suggest or hint me why and what to do? 

Attached file is my zip file of QSYS. 

 

 

# include <stdio.h># include "system.h"# include "altera_avalon_pio_regs.h" 

 

unsigned int LED_TOGGLE = 0; 

unsigned char *pData = ONCHIP_MEMORY2_1_BASE; 

 

int main() 

int i = 0; 

printf("Hello from Nios II!\n"); 

while(1) 

IOWR_ALTERA_AVALON_PIO_DATA(LED_PIO_BASE,LED_TOGGLE); 

LED_TOGGLE = ~LED_TOGGLE; 

//*pdata = i++; 

 

return 0; 

}
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9 Replies
Altera_Forum
Honored Contributor I
22 Views

Use NIOS /f and compile without debug information and with optimizations

Altera_Forum
Honored Contributor I
22 Views

How are you measuring the time?

Altera_Forum
Honored Contributor I
22 Views

Hi, I use scope[logic analysis] and connect the LED output. 

And comment / dis-comment the line of [write data]. check time difference between comment and dis-comment.
Altera_Forum
Honored Contributor I
22 Views

What is your clock speed ?  

I presume much faster than 1MHz.
Altera_Forum
Honored Contributor I
22 Views

According to my QSYS, 

All components[including NiosII] are connected to clk and it is default for 50Mhz.
Altera_Forum
Honored Contributor I
22 Views

>> All components[including NiosII] are connected to clk and it is default for 50Mhz. 

 

Ok, good.  

Another thing to try is to instrument Nios with SignalTap and see what instructions it executes in that slow line of code. See the following document, page 17: 

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/an/an446.pdf
Altera_Forum
Honored Contributor I
22 Views

Count the instructions in the loop: 

1) Read of LED_TOGGLE for the io_write 

2) Write of LED_TOGGLE to the hardware 

3) Read of LED_TOGGLE for the invert 

4) the invert inself 

5) Write back of LED_TOGGLE 

6) Unconditional branch 

IIRC a nios/e takes 5 clocks per instruction - so that is at least 30 clocks. 

The constant LED_PIO_DATA_BASE might also be created each loop iteration. 

 

Add in any extra clocks for the avalon write caused by your slave itself. 

 

Make LED_TOGGLE a local variable (so it can be assigned to a register). 

Compile with -O2 so that the compiler moves some calculations outside the loop. 

That should get you to a three instruction loop.
Altera_Forum
Honored Contributor I
22 Views

Thanks for all suggestion. 

Because my Quartus II/NiosEDS is web edition, some option does not appear like optimization and version of Nios. 

I select subscription edition of Quartus, choose Nios/F and select opt to O2 or O3. 

It seems to get better performance. 

 

Thanks a lot for everyone.
Altera_Forum
Honored Contributor I
22 Views

actually, i am still wondering what do toy mean by slowly..

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