I have a design which I want to connect a DDR3 controller (DDR3 SDRAM Controller with UniPHY) to an Avalon-MM Pipeline Bridge, then the bridge connects with the nios II. (Nios <-----> Bridge <-----> DDR3)After I configure the DDR3 controller, the data width in the avalon MM interface is 256. But the bridge data width I set is 32. It is obvious their data width doesn't match, but the qsys still allows me to connect them and after I connect them, there is no error appear to say their width is mismatch. I am confused why? Why the bridge can accept the slave which has the different data width? Thanks in advance.
--- Quote Start --- Read this document to gain a better understanding of what you are telling Qsys to do: http://www.altera.com/literature/hb/qts/qsys_interconnect.pdf Adapting mismatched widths is a feature. --- Quote End --- Thanks. I did skim the file quickly but I didn't notice it. I will read it carefully again.
One can suspect that, behind the scenes, QSYS will connect the lower order address bits of the 32 bit wide interface to the byte enable signals on the 256 bit interface. However, it might be a good idea to look at the generated files and verify what is actually occurring.