I have been trying to get an external SRAM chip to work with Nios II for over two weeks with no success. I have tested the SRAM outside of SOPC Builder with a simple VHDL routine that writes to each address then reads back the SRAM data. I used SignalTap to verify that all address and data lines are working.I also instantiated the SRAM as a custom memory component in SOPC Builder - first with only a JTAG Master and JTAG UART, and then with a simple Nios II system. In both case I can access the SRAM component with System Console and it seems to work fine. However, in the Nios II system, I have to stop the processor to run System Console. Is this normal? My BIG problem is that I cannot get Nios II to work with the external SRAM component. Specifically, downloading the ELF file fails. I am now wondering if it is because the SRAM has a 16-bit data bus. Do I need to design an HDL component to adapt the 32-bit Nios II data bus to the SRAM 16-bit data bus, or does SOPC Builder/Avalon/Nios II do that for me? Daixiwen, thepancake, I have read a lot of your posts. From what I've seen you guys must know how to instantiate a simple 16-bit external SRAM component. Can you or someone else please help me? Many thanks in advance, fheineman
Sure it works with 16bit wide SRAM!You connect SRAM to Nios through a tristate bridge. If the SRAM component is specified as 16bit-data-wide, sopc builder will generate the correct logic to interface properly to Avalon bus.
Great news! Thanks Cris72 for you quick reply.Originally I set up the custom SRAM component with a 16-bit data bus, but it doesn't work. Do you have any suggestions why I can access the custom memory component with System Console but not with Nios II? (Actually my problem is that I cannot download the ELF file, and I am assuming that it is because Nios II is not working with my custom SRAM. Perhaps this is not really the case.) I see a lot of folks on the forum having trouble downloading the ELF file through Eclipse.
Did you connect SRAM (I mean tristate bridge) both to Nios data- and instruction-master?Maybe you connected only to data-master and this would explain your problem.
I can't see any attachment.Anyway, what do you mean when you say you cannot download the elf file? Do you get an error from jtag debugger or does the program load but it doesn't run?
Sorry about the attachment. It should be here now. I also attached the error log file.I get an error message in Eclipse when I try to run the Hello_World program saying that Downloading ELF file process failed. I can see in the Eclipse console that it tries to write to the SRAM, but verification fails.
Among the software templates there is a memory test software. You should compile it and run it in on-chip memory (you'll probably have to increase the on-chip memory size, enable optimisations and the small C library). From there you can have it test the sram.
--- Quote Start --- Hello, What about your system frequency vs the SRAM speed grade ? Regards, Franck. --- Quote End --- sys_clk 50MHz, SRAM speed grade 10ns.
Good point on the SRAM speed grade. The one I am using is 45ns. This does not seem to be an issue as I have configured the timing - first in a custom component in SOPC Builder, and more recently in the Qsys Generic Tri-State Controller to slow down the interface to the external SRAM. This, by the way, is a very nice feature in Qsys. It takes a lot of the hassle out of interfacing to slow peripheral components.Anyway, I finally discovered that the problem I was having in Eclipse of not being able to download an elf file was due to something else and not the SRAM. A note to those trying to interface external SRAM, Qsys uses the address lines as though it were addressing bytes, not words. If your external SRAM is 16-bit, the LSB of the Qsys address is held low. The SRAM chip I'm using expects word addressing, so I did not connect the LSB (bit ) of the Qsys SRAM address.
hiI want use avalon to external bridge in the sopc builder, but i am unable to see the avalon to external bridge.. can anyone clarify what is the problem..?
Hi.I had the same problem, when I used a SDRAM controller. I made a research, I discovered that the problem was the SDRAM chip timing. The SDRAM delays 3ns to response. So I configured a PLL with 2 clock outputs, one clock (c0) normal with 50MHz for output without delay and an another clock (c1) with 50MHz for output and 3ns delay. I connected the c1 to the NIOS II clock and the c0 to SDRAM clock. I'm using a DE0-Nano Board from terasic "Sorry about my english, I've been learning just over on year."