I am working on a baremetal design in which 4 on-chip Memory(RAM) should be connected to the HPS (Arria 10 HPS). I use memory IPs available in Qsys and connect them to h2f_axi_master. The memories are 32 bit width of the size 4096 bytes. The problem is that when I write ,for instance, on second memory after a certain address the first memory is also written, or sometimes, by re designing the qsys, while writing the second memory the first memory is written simultaneously until a certain memory location. To be more clear, all memory base addresses are automatically generated using the Quartus scripts, and they are added to H2f bridge address to get the exact physical addresses.I tried several approaches such as; using Pipeline bridge, re-configuring the bootloader. putting "nop" between consecutive memory writes, and probing,via signal tap, the Avalon signals; which indicates undesirable high value on first memory while the second memory is supposed to be written. What is the problem? should I use any particular bridge or arbiter? (sorry for posting the thread under a wrong subject, I cannot move it to other topics).