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Altera_Forum
Honored Contributor I
768 Views

Writing to SRAM

Hi everyone, 

 

Does anyone have a tutorial that shows me how to write to Memory using SOPC?  

 

Thanks
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6 Replies
Altera_Forum
Honored Contributor I
37 Views

 

--- Quote Start ---  

 

Does anyone have a tutorial that shows me how to write to Memory using SOPC?  

 

--- Quote End ---  

This one shows you how to use on-chip SRAM. 

 

http://www.alterawiki.com/wiki/using_the_usb-blaster_as_an_sopc/qsys_avalon-mm_master_tutorial 

 

The PDF has an appendix with links to Altera's online resources. 

 

For external memory interfaces you can read: 

 

http://www.altera.com/literature/lit-external-memory-interface.jsp 

 

For external SRAM, look at the tri-state bridge component. 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
37 Views

Thanks Dave, you are the best. 

In your opnion, what is the best way to write to SRAM on DE2 board? 

 

Here is what I did. I established an RS232 commuincation between PC and the Board and It was great. However, the RS232 program such as HyperTerminal, PuTTY, and Tera Time are not realiable! Sometimes I can transfer a whole file o.k and other times I can't ?!!! 

what is your advice? Please help. 

Mona 

 

Many Thanks :)
Altera_Forum
Honored Contributor I
37 Views

 

--- Quote Start ---  

 

I established an RS232 commuincation between PC and the Board and It was great. However, the RS232 program such as HyperTerminal, PuTTY, and Tera Time are not realiable! Sometimes I can transfer a whole file o.k and other times I can't ?!!! 

 

--- Quote End ---  

 

 

Can you confirm that its the PC that is the problem? Perhaps it is the FPGA. If the RS232 interface does not implement the CTS/RTS handshake wires, then you could be overrunning your buffers in the FPGA. What is processing your RS232 data; is it a state machine, or a NIOS II processor? 

 

The tutorial I linked to shows how to use the JTAG interface to implement access to the board. Using master_write_memory and master_read_memory within system console, you can get about 600kbps (73kB/s) transfer rate. 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
37 Views

 

--- Quote Start ---  

Can you confirm that its the PC that is the problem? Perhaps it is the FPGA. If the RS232 interface does not implement the CTS/RTS handshake wires, then you could be overrunning your buffers in the FPGA. What is processing your RS232 data; is it a state machine, or a NIOS II processor? 

 

The tutorial I linked to shows how to use the JTAG interface to implement access to the board. Using master_write_memory and master_read_memory within system console, you can get about 600kbps (73kB/s) transfer rate. 

 

Cheers, 

Dave 

--- Quote End ---  

 

 

Hi Dave, 

Thanks again for your help. 

 

Well, I am using a State Machine not NIOS. This is why I want to switch to NIOS maybe I will be get a better luck. I am not implementing any handshake protocol ! 

I am just using an 115200 8N1 with no applied protocol! Is this bad? 

Here is my code (its a code I got from the net :oops: ) 

 

module async_receiver(clk, RxD, RxD_data_ready, RxD_data, RxD_endofpacket, RxD_idle); 

input clk, RxD; 

output RxD_data_ready; // onc clock pulse when RxD_data is valid 

output [7:0] RxD_data; 

parameter ClkFrequency = 100000000; // 50MHz 

//parameter ClkFrequency = 27000000; // 27MHz 

parameter Baud = 115200; 

//parameter Baud = 9600; 

// We also detect if a gap occurs in the received stream of characters 

// That can be useful if multiple characters are sent in burst 

// so that multiple characters can be treated as a "packet" 

output RxD_endofpacket; // one clock pulse, when no more data is received (RxD_idle is going high) 

output RxD_idle; // no data is being received 

// Baud generator (we use 8 times oversampling) 

parameter Baud8 = Baud*8; 

parameter Baud8GeneratorAccWidth = 16; 

parameter Baud8GeneratorInc = ((Baud8<<(Baud8GeneratorAccWidth-7))+(ClkFrequency>>8))/(ClkFrequency>>7); 

reg [Baud8GeneratorAccWidth:0] Baud8GeneratorAcc; 

always @(posedge clk) Baud8GeneratorAcc <= Baud8GeneratorAcc[Baud8GeneratorAccWidth-1:0] + Baud8GeneratorInc; 

wire Baud8Tick = Baud8GeneratorAcc[Baud8GeneratorAccWidth]; 

//////////////////////////// 

reg [1:0] RxD_sync_inv; 

always @(posedge clk) if(Baud8Tick) RxD_sync_inv <= {RxD_sync_inv[0], ~RxD}; 

// we invert RxD, so that the idle becomes "0", to prevent a phantom character to be received at startup 

reg [1:0] RxD_cnt_inv; 

reg RxD_bit_inv; 

always @(posedge clk) 

if(Baud8Tick) 

begin 

if( RxD_sync_inv[1] && RxD_cnt_inv!=2'b11) RxD_cnt_inv <= RxD_cnt_inv + 1; 

else  

if(~RxD_sync_inv[1] && RxD_cnt_inv!=2'b00) RxD_cnt_inv <= RxD_cnt_inv - 1; 

if(RxD_cnt_inv==2'b00) RxD_bit_inv <= 0; 

else 

if(RxD_cnt_inv==2'b11) RxD_bit_inv <= 1; 

end 

reg [3:0] state; 

reg [3:0] bit_spacing; 

// "next_bit" controls when the data sampling occurs 

// depending on how noisy the RxD is, different values might work better 

// with a clean connection, values from 8 to 11 work 

wire next_bit = (bit_spacing==10); 

always @(posedge clk) 

if(state==0) 

bit_spacing <= 0; 

else 

if(Baud8Tick) 

bit_spacing <= {bit_spacing[2:0] + 1} | {bit_spacing[3], 3'b000}; 

always @(posedge clk) 

if(Baud8Tick) 

case(state) 

4'b0000: if(RxD_bit_inv) state <= 4'b1000; // start bit found? 

4'b1000: if(next_bit) state <= 4'b1001; // bit 0 

4'b1001: if(next_bit) state <= 4'b1010; // bit 1 

4'b1010: if(next_bit) state <= 4'b1011; // bit 2 

4'b1011: if(next_bit) state <= 4'b1100; // bit 3 

4'b1100: if(next_bit) state <= 4'b1101; // bit 4 

4'b1101: if(next_bit) state <= 4'b1110; // bit 5 

4'b1110: if(next_bit) state <= 4'b1111; // bit 6 

4'b1111: if(next_bit) state <= 4'b0001; // bit 7 

4'b0001: if(next_bit) state <= 4'b0000; // stop bit 

default: state <= 4'b0000; 

endcase 

reg [7:0] RxD_data; 

always @(posedge clk) 

if(Baud8Tick && next_bit && state[3]) RxD_data <= {~RxD_bit_inv, RxD_data[7:1]}; 

reg RxD_data_ready, RxD_data_error; 

always @(posedge clk) 

begin 

RxD_data_ready <= (Baud8Tick && next_bit && state==4'b0001 && ~RxD_bit_inv); // ready only if the stop bit is received 

RxD_data_error <= (Baud8Tick && next_bit && state==4'b0001 && RxD_bit_inv); // error if the stop bit is not received 

end 

reg [4:0] gap_count; 

always @(posedge clk) if (state!=0) gap_count<=0; else if(Baud8Tick & ~gap_count[4]) gap_count <= gap_count + 1; 

assign RxD_idle = gap_count[4]; 

reg RxD_endofpacket; always @(posedge clk) RxD_endofpacket <= Baud8Tick & (gap_count==15); 

endmodule 

 

Pleasae let me know
Altera_Forum
Honored Contributor I
37 Views

 

--- Quote Start ---  

 

Well, I am using a State Machine not NIOS. This is why I want to switch to NIOS maybe I will be get a better luck. I am not implementing any handshake protocol ! 

I am just using an 115200 8N1 with no applied protocol! Is this bad? 

 

--- Quote End ---  

 

 

That should work fine. 

 

 

--- Quote Start ---  

 

Here is my code (its a code I got from the net :oops: ) 

 

--- Quote End ---  

 

 

Its very difficult to read code and see bugs (other than the obvious). You should really create a simulation and see if the code responds correctly to serial characters on its input and generates them on its output. 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
37 Views

 

--- Quote Start ---  

That should work fine. 

 

 

 

Its very difficult to read code and see bugs (other than the obvious). You should really create a simulation and see if the code responds correctly to serial characters on its input and generates them on its output. 

 

Cheers, 

Dave 

--- Quote End ---  

 

 

Thanks Dave, you are the best :) 

 

I have tested the transfer with few characters, it works perfect. The problem is when I transfer a big file. Sometimes, it works fine and transfer 100% of the file. Sometimes, it transfer 80% of the file?!! 

 

so I think I want to switch to Nios, let me try the tutorial link you sent me and get back to you on this. 

 

Mona
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