Consulting:
http://www.altera.com/literature/ug/ug_altasmi_parallel.pdf I have implemented the timing on page 11/ figure 11 (aka; Example 2)
I have the PAGE_SIZE parameter set to 256 and thus I have 256 shift_bytes/wren/datain
toggles before later asserting write/wren/addr after which busy is asserted for many cycles
thereafter indicating a write to the EPCS.
Problem is I read back the data as all 0xFF's.
Prior to implementing page writes I performed single writes (disabled page writes
in the mega fcn) and this worked (but took a long time naturally).
Any ideas why page writes not working here?
Is Figure 11 timing correct?
I presume this is still a page size of 8 but only the first four bytes written with the rest
left as 0xFFs.
Does wren need to be asserted through the whole page write(and not toggle)?
Using EPCS128.
Thanks,
Cos
