arria II development board TSE configuration

[Altera_Forum]

Hi, I am quite new here. I am trying to run iniche tcpip stack on the provided Ethernet port(altera TSE MAC connected to Marvell PHY though RGMII). I have enabled MDIO in TSE MAC. 

 Everything building fine, I download the firmware, without any NIOS application running, none of the LED is on(there are 1000/100/10 indicate LED is directly connected to Marvell PHY :( )  When I load the software, it stuck at the tse_mac_init, it seems the initilization found the phy on each single address :( and could not identify any of them,(there is only one PHY in the system) [tse_mac_init] INFO : TSE MAC 0 found at address 0x09002000 WARNING : Unknown PHY found at PHY address 0x00 of MAC Group[0] WARNING : Please add PHY information to PHY profile INFO : PHY[0.0] - Automatically mapped to tse_mac_device[0] INFO : PHY[0.0] - Restart Auto-Negotiation, checking PHY link... INFO : PHY[0.0] - Auto-Negotiation PASSED MARVELL : Mode changed to RGMII/Modified MII to Copper mode MARVELL : Enable RGMII Timing Control MARVELL : PHY reset WARNING : Unknown PHY found at PHY address 0x01 of MAC Group[0] WARNING : Please add PHY information to PHY profile WARNING : PHY[0.X] - Mapping of PHY to MAC failed! Make sure the PHY address is defined correctly in tse_mac_device[] structure, and number of PHYs connected is equivalent to number of channel WARNING : Unknown PHY found at PHY address 0x02 of MAC Group[0] WARNING : Please add PHY information to PHY profile WARNING : PHY[0.X] - Mapping of PHY to MAC failed! Make sure the PHY address is defined correctly in tse_mac_device[] structure, and number of PHYs connected is equivalent to number of channel WARNING : Unknown PHY found at PHY address 0x03 of MAC Group[0] WARNING : Please add PHY information to PHY profile   The Qsys design is quite similar to the reference design from altera net, 2 sg-DMA conneted to PHY use a dedicated two port RAM memory as descriptoer memory.use a bridge connected the rest of the MM slave. and uses the master clock which is 100M Hz  the top level connection is:  -- Ethernet  ethernet_rgmii_in => Rgmii_in,  ethernet_rgmii_out => Rgmii_out,   ethernet_rx_control => Rgmii_rx_ctl,   ethernet_tx_control => Rgmii_tx_ctl,  ethernet_tx_clk => Rgmii_tx_clk,  ethernet_rx_clk => Rgmii_rx_clk,   -- -- -- --  -- MDIO  ethernet_mdio_out => mdio_out,  ethernet_mdio_oen => mdio_oen,  ethernet_mdio_in => ENET_MDIO,  ethernet_mdc => ENET_MDC   Apart from mdio_out and mdio_oen(two internal signals, the rest is dirrect connected to FPGA Pins) the defind of MDIO out is: ENET_MDIO <= mdio_out when (mdio_oen = '0') else ('Z');  ENET_Phy_Rst_n is permenant set to '1', I have tried '0' it makes no different.  Any silly mistake I have made? Thanks for your help in advance.