I would like to write data into external DDR3 through UNIPHY DDR3 IP. I need to write data into UNIPHY DDR3 IP through avalon MM bus. Figure below are the simulation generate using MODELSIM with the avalon MM bus I interface with. However, I notice that my data are fail to be written into the ddr3 interface. May I know what's wrong with my avalon bus interface as shown figure below? How long should I assert the burstbegin signal? http://www.alteraforum.com/forum/attachment.php?attachmentid=10433&stc=1 Thanks!