Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Altera_Forum
Honored Contributor I
1,492 Views

avalon fifoed uart - problem with baudrate setting

Hi, 

I am setting the baudrate as 115200 but the actual baudrtae looks to be 9600. any ideas? 

 

 

i am trying to add printf to check what is happening in altera_uart.c with pr_err in altera_uart_set_termios function but not seeing any thing on the console. I have hooked the console to jtag uart. 

 

Any ideas Please? 

 

I am using latest 20100621 tarball without any git updates.
0 Kudos
7 Replies
Altera_Forum
Honored Contributor I
43 Views

Do you have a CCB between your nios and your UART ?

Altera_Forum
Honored Contributor I
43 Views

 

--- Quote Start ---  

Do you have a CCB between your nios and your UART ? 

--- Quote End ---  

 

 

Thanks a lot for your reply. For now i don't know any thing about Clock Control Block. I will find out.
Altera_Forum
Honored Contributor I
43 Views

CCB mean Clock Crossing Bridge not a Clock Control Block. 

Do you have a Clock Crossing Bridge between your Nios and you UART ?
Altera_Forum
Honored Contributor I
43 Views

I had an issue with Qsys in Quartus v11.0 generating HDL with an incorrect baud rate divisor when using the "UART (RS-232 Serial Port)" component.  

 

This problem seems to have been fixed in v11.0 SP 1.
Altera_Forum
Honored Contributor I
43 Views

 

--- Quote Start ---  

CCB mean Clock Crossing Bridge not a Clock Control Block. 

Do you have a Clock Crossing Bridge between your Nios and you UART ? 

--- Quote End ---  

 

 

I understand. I do not know much here. I was informed that all devices are clocked by CPU CLOCK.
Altera_Forum
Honored Contributor I
43 Views

 

--- Quote Start ---  

I had an issue with Qsys in Quartus v11.0 generating HDL with an incorrect baud rate divisor when using the "UART (RS-232 Serial Port)" component.  

 

This problem seems to have been fixed in v11.0 SP 1. 

--- Quote End ---  

 

 

Looks like that. 

 

Either IP problem or some kind of initialization problem of the core in FPGA.
Altera_Forum
Honored Contributor I
43 Views

I have removed my comments as I found the actual problem, it is not in earlyprintk. 

 

The actual problem is different constant defines used at many many places of initial console code.  

 

Now I fixed at the right place, nios.h