Hi,
I am setting the baudrate as 115200 but the actual baudrtae looks to be 9600. any ideas? i am trying to add printf to check what is happening in altera_uart.c with pr_err in altera_uart_set_termios function but not seeing any thing on the console. I have hooked the console to jtag uart. Any ideas Please? I am using latest 20100621 tarball without any git updates.Link Copied
Do you have a CCB between your nios and your UART ?
--- Quote Start --- Do you have a CCB between your nios and your UART ? --- Quote End --- Thanks a lot for your reply. For now i don't know any thing about Clock Control Block. I will find out.
CCB mean Clock Crossing Bridge not a Clock Control Block.
Do you have a Clock Crossing Bridge between your Nios and you UART ?I had an issue with Qsys in Quartus v11.0 generating HDL with an incorrect baud rate divisor when using the "UART (RS-232 Serial Port)" component.
This problem seems to have been fixed in v11.0 SP 1.--- Quote Start --- CCB mean Clock Crossing Bridge not a Clock Control Block. Do you have a Clock Crossing Bridge between your Nios and you UART ? --- Quote End --- I understand. I do not know much here. I was informed that all devices are clocked by CPU CLOCK.
--- Quote Start --- I had an issue with Qsys in Quartus v11.0 generating HDL with an incorrect baud rate divisor when using the "UART (RS-232 Serial Port)" component. This problem seems to have been fixed in v11.0 SP 1. --- Quote End --- Looks like that. Either IP problem or some kind of initialization problem of the core in FPGA.
I have removed my comments as I found the actual problem, it is not in earlyprintk.
The actual problem is different constant defines used at many many places of initial console code. Now I fixed at the right place, nios.hFor more complete information about compiler optimizations, see our Optimization Notice.