Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Altera_Forum
Honored Contributor I
1,216 Views

cache not enable

Dear all, 

 

I have some questions about the U-boot. The hardware board is designed by myself. The SoC is 10AS016E4F27E3SG. 

 

I run the Bootloader on the board and print the following information: 

 

U-Boot 2014.10 (Apr 20 2018 - 13:44:44) 

 

 

CPU : Altera SOCFPGA Arria 10 Platform 

BOARD : Altera SOCFPGA Arria 10 Dev Kit 

I2C: ready 

DRAM: WARNING: Caches not enabled 

SOCFPGA DWMMC: 0 

FPGA: writing output_file.rbf ... 

Full Configuration Succeeded. 

emif_reset interrupt acknowledged 

emif_reset interrupt acknowledged 

emif_reset interrupt acknowledged 

Error: Could Not Calibrate SDRAM 

DDRCAL: Failed 

INFO : Skip relocation as SDRAM is non secure memory 

Reserving 2048 Bytes for IRQ stack at: ffe386e8 

DRAM : 0 Bytes 

data abort 

pc : [<ffe001cc>] lr : [<ffe024cd>] 

sp : ffe3fff0 ip : 00000016 fp : 00000001 

r10: ffd02078 r9 : ffe38ee8 r8 : ffe00000 

r7 : ffe20444 r6 : 00000000 r5 : 00000000 r4 : ffeff000 

r3 : ffe38faf r2 : ffe40000 r1 : ffe3b000 r0 : ffe38ee8 

Flags: nzcv IRQs on FIQs on Mode SVC_32 

Resetting CPU ... 

 

 

resetting ... 

 

Why is the cache not enabled?
0 Kudos
2 Replies
Altera_Forum
Honored Contributor I
118 Views

I'm not sure not having the cache enable at such an early point in the boot process is really a problem. I think the real problem is the SDRAM calibration that failed. You can compile a new version of the preloader wich will give you more output on the calibration process and where it fails, by changing the RUNTIME_CAL_REPORT to 1 in uboot-socfpga/board/altera/socfpga/sdram/sequencer_defines.h and recompiling it. 

Have a look at https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/external-memory/emi_ip... sections 17.4 and 17.5 for more information on how to debug calibration failures.
Altera_Forum
Honored Contributor I
118 Views

Thank you very much for your reply.I changed RUNTIME_CAL_REPORT to 1 according to your method&#65292;but I could not also calibrate SDRAM.The error message is consistent.I found that I didn't place the PLL reference clock pin in the address/command bank.Through the reference design I found that the PLL-ref-clock should be a differential clock,but I didn't connect the differential clock outside BANK 2K( address/command bank).Is this the reason twhy I can't calibrate DDR?In this case, what suggestions can be set to generate pll_ref_clk clock, so as to achieve the DDR3 read and write control.