Re: can't boot from epcs to external sram

Altera_Forum · ‎03-18-2010

Hello,

I have a problem while booting a niosII program from epcs4 to external external sram (1Mx16bit).

My sopc system is composed of the following parts:

1) niosII processor,

with reset vector at epcs controller, and exception vector at on-chip memory;

2) 30KBytes on-chip memory;

3) epcs controller;

4) Tri-state bridge;

5) 1Mx16bits SRAM controller.

The byte_enable pin of my sram chip is always enabled.

6) PIO for leds.

My program is just to let the leds runing.

well, the problem is:

1) If the program is linked to on-chip memory, everything works fine (Both in debug mode and "Power Down Doesn't Lose" mode).

2) If it is linked to my external sram,

It runs well in debug mode, by clicking "Run Configuration" in the niosII IDE.

but, when I load the sof and elf file to epcs and then repower my board, the program doesn't run anymore.

It seems that the bootloader in epcs controller can't copy codes from epcs to external sram.

Or there are something else I didn't notice.

Can anybody help me out?

Regards.

Altera_Forum · ‎03-18-2010

the main difference is that if destination memory is onchip every thing works, if the destination is offchip it wount work, am i right ?

the epcs memory is accessed as byte memory 8bit, your external memory is 16bit and the byte enable is always enabled. i have looked into the epcs boot memory code and it seems the copy routine does copy byte by byte and therefore with enabled 16bit access the destination memory gets some kind of overwritten / corrupted.

epcs_copy_loop:
    // Wait until an RX-character is available
    ldwio   rf_temp, EPCS_STATUS_OFFSET (r_epcs_base_address)
    andi    rf_temp, rf_temp, EPCS_STATUS_RRDY_MASK
    beq     rf_temp, r_zero, epcs_copy_loop
    // grab the RX-character, and immediately ask for another one
    //   no need to wait for TX ready, if RX is ready, then TX is too
    ldwio   rf_temp, EPCS_RXDATA_OFFSET (r_epcs_base_address)
    stwio   r_zero, EPCS_TXDATA_OFFSET (r_epcs_base_address)
    // store the character we retrieved, and update the destination ptr
    stbio   rf_temp, 0(r_dest)
    addi    r_dest, r_dest, 1
    // loop until the destination == the ending address
    bne     r_dest, r_dest_end, epcs_copy_loop

the stbio is the command that stores the date byte by byte.

i guess you need to attach the byteenables to your design and not tie them to always enabled.

Altera_Forum · ‎03-18-2010

Thanks for your advice.

My board has already been designed like this, and it's not easy to change.

I will try to use a 8-bit sram controller, and treat my sram as 8-bit width.

I will post my results.

Altera_Forum · ‎03-18-2010

MSchmitt, you're so smart! Without your hint, I would never find a clue out from the complex asm codes.

Just as what you have said, the default boot loader can't access 16-bits srams.

After I transform my sram to 8-bit width, everything is ok.

Thanks for your rapid help. Well, to help others avoid making the same mistakes that I have made while programing epcs, I'd like to list my mistakes:

1) Forgot assigning AS pins as regular IO, which is necessary for cyclone III.

2) Use JTAG other than AS mode;

3) The problem described in this post.

Altera_Forum · ‎03-18-2010

You're welcome :-)

Altera_Forum · ‎09-07-2012

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