Nios® II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
12452 Discussions

core voltage analysis after dumping the logic into LABs

Honored Contributor II


I am trying to analyze the core voltage behavior in Cyclone-III FPGA. I want to check the core voltage behavior after dumping the logic into different LABs in Cyclone-III FPGA and using a different core voltage supply for each core voltage pin. If iam changing the LABs location the voltage of power supplies are changing but i am not be able to differentiate the core area that if i am putting the design in a specific area then it will take the power or current from a perticular supply.  

so if anybody is having a these type of results plz send it to me. 


0 Kudos
0 Replies