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cyclone V static power

Honored Contributor II

We recently designed and built a new PCB with a Cyclone V part on it. 

The part we used is 5CEFA7U19I7N. 


We are seeing static power consumption that is around 4x  

the "typical" amount predicted by the early power estimate. 

Our power consumption more closely matches the "maximum" current 

draw listed in the early power estimate. 


We are testing a design that uses a single flip flop as a baseline. 

The design just drives a single pin high. It does nothing else. 


So the early power predictors shows a "typical" power consumption of 100mW 

for this design and a "maximum" power consumption of 400mW. 

We have tested 14 of our boards (all identical) and they all draw close to the maximum power. 

We also ran the same design on a development kit and tested the power draw 

and it matched the 400mW we were seeing on our PCB, so 

we know it's not a problem with our board. 



It seems like "typical" power estimates from the EPE  

are not correct for Cyclone V chips. 

All of our testing suggests that power consumption is around 4x what is advertised. 


Our application is very power sensitive and this is a huge problem for us. 


Has anyone else experienced what we are seeing? 

Is this a problem with the current batch of Cyclone V chips that is going 

to be fixed in the future?
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7 Replies
Honored Contributor II

Here is what Altera has to say about this: 


Q: The ratio of max to typical power seems higher than expected. Is that expected? Why or why not? 


A: Cyclone V FPGAs, as low cost products, are optimized for lowest cost. To achieve the maximum yield, and therefore the lowest cost, Altera expands the "passing window" for maximum static power, on either side of typical power, as wide as possible during production test. This is possible without impacting Cyclone V FPGAs' low maximum static power, because of the very low typical power of Cyclone V FPGAs. 


The static power should pull in as the 28nm-LP process matures but you would still need to design to the max spec.
Honored Contributor II

"Passing window" might explain the issue. Nevertheless, are you sure that are you actually measuring static power? Means: no floating pins, no clocks running, no pins sourcing current to a load or an unintended short?

Honored Contributor II

Hi all, 


I have the same issue with altera Cyclone V GX development kit. When clock is stopped ( 0 Mhz ) measured power consumption (measured by external CPLD) ~420 mW. Power consumption of unconfigured device ~300mW. This is much more then all estimations of EPE or Power play (with the same design).  

Any sugesstions???  

Thanks in advance, 

Honored Contributor II

I am absolutely sure we are measuring static power. 

I just got confirmation from a personal contact at a large defense contractor that they are seeing the same problems. 

They said in an email to me: 


Power consumption is a BIG issue.  

Altera has been prescreening parts in order to meet the power specifications as they were specified initially.  

Supposedly Altera is having problems with yield/process variation. 

The 2.5 VCCaux that powers the configuration memory seems to be a major culprit.  

This voltage rail is drawing substantially more current than advertized originally.  

Altera is definitely aware of the issue, you have to alert them that you are having problems.
Honored Contributor II

I agree, that at least the power consumption of the unconfigured device is purely static power.

Honored Contributor II

A colleague mentioned that perhaps the observed behavior is due to the issue "Usermode High Icc" in the errata? 

Maybe try v13 tools.
Honored Contributor II

Already aware of this errata. Have tried v13 tools and still seeing very high current draw.