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Altera_Forum
Honored Contributor I
850 Views

ddr3 sdram controller (UniPHY) afi_half_clk doesn't work but status signals work fine

I have build a qsys system, that niosII connects a mm bridge then connects with ddr3 controller. I use afi_clk to drive the nios II. And then I export the afi_half_clk to external qsys to drive a counter, which msb connects a led. 

 

Then I program the FPGA with the design. I can see ddr3 status signals good. Both init_done and cal_done assert. But the led is driven by afi_half_clk doesn't blink. Meanwhile, I run a hello_world program in the FPGA, it works. "Hello World" is printed in JTAG console. Nios is driven by afi_clk. So it looks like afi_clk is working. But when I try to write and read the ddr3 through program: 

# include <stdio.h># include "..\hello_world_bsp\HAL\inc\io.h"# include "..\hello_world_bsp\system.h" 

 

 

int main() 

 

 

printf("Hello from Nios II!\n"); 

 

 

unsigned int readVal; 

IOWR_32DIRECT(DDR3_72_BASE, 0x08, 1); 

readVal = IORD_32DIRECT(DDR3_72_BASE, 0x08); 

printf("The value read back is %u", readVal); 

 

 

return 0; 

 

It gives me the error "Downloading ELF Process failed". This error doesn't bring any information but it seems indicate the hardware error. So how it can be that the status signals are fine and afi_clk is working, but afi_half_clk is not toggling? 

 

I also attached my qsys system screenshot. If anyone has any idea, please give some hints. Thanks in advance.
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5 Replies
Altera_Forum
Honored Contributor I
47 Views

Sp finally I figure out that is the onchip ram is not big enough for the elf file. So actually DDR3 controller is working properly. But I still don't know why afi_half_clk doesn't toggle.

Altera_Forum
Honored Contributor I
47 Views

As I recall, there was a defect in an earlier quartus release where the afi_half_clk was left disconnected inside the UNIPHY IP even if one selected the "enable afi half clock" check box. I have recently observed that the UNIPHY afi half clock was working correctly in quartus 13.1. IMHO, perhaps Altera could improve quality control if it was easier for customers to select the IP release independently of the quartus release.

Altera_Forum
Honored Contributor I
47 Views

 

--- Quote Start ---  

As I recall, there was a defect in an earlier quartus release where the afi_half_clk was left disconnected inside the UNIPHY IP even if one selected the "enable afi half clock" check box. I have recently observed that the UNIPHY afi half clock was working correctly in quartus 13.1. IMHO, perhaps Altera could improve quality control if it was easier for customers to select the IP release independently of the quartus release. 

--- Quote End ---  

 

 

Thanks for reply. However, what I use is Quartus 13.1. And it seems there is no option in DDR UNIPHY IP to configure enable or disable "afi half clock". In your design, do you configure it to enable the half clock? 

 

Thanks.
Altera_Forum
Honored Contributor I
47 Views

Yes, via the "enable half rate clock" check box. I also enable the half rate configuration for the DDR2 controller.

Altera_Forum
Honored Contributor I
47 Views

 

--- Quote Start ---  

Yes, via the "enable half rate clock" check box. I also enable the half rate configuration for the DDR2 controller. 

--- Quote End ---  

 

 

You are correct. After I tick the check box and regenerate the files, then the half rate clock toggle in my design properly. Thanks very much.
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